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Unformatted text preview: . seen by processes running in ARM Linux) will range between 0x00000000 and 0xBFFFFFFF. Peripherals (at physical address 0x20000000 on) are mapped into the kernel virtual address space starting at address 0xF2000000. Thus a peripheral advertised here at bus address 0x7Ennnnnn is available in the ARM kenel at virtual address 0xF2nnnnnn. 1.2.3 ARM physical addresses Physical addresses start at 0x00000000 for RAM. The ARM section of the RAM starts at 0x00000000. The VideoCore section of the RAM is mapped in only if the system is configured to support a memory mapped display (this is the common case). The VideoCore MMU maps the ARM physical address space to the bus address space seen by VideoCore (and VideoCore peripherals). The bus addresses for RAM are set up to map onto the uncached1 bus address range on the VideoCore starting at 0xC0000000. Physical addresses range from 0x20000000 to 0x20FFFFFF for peripherals. The bus addresses for peripherals are set up to map onto the peripheral bus address range starting at 0x7E000000. Thus a peripheral advertised here at bus address 0x7Ennnnnn is available at physical address 0x20nnnnnn. 1.2.4 Bus addresses The peripheral addresses specified in this document are bus addresses. Software directly accessing peripherals must translate these addresses into physical or virtual addresses, as described above. Software accessing peripherals using the DMA engines must use bus addresses.
1 BCM2835 provides a 128KB system L2 cache, which is used primarily by the GPU. Accesses to memory are routed either via or around the L2 cache depending on senior two bits of the bus address. Page 6 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Software accessing RAM directly must use physical addresses (based at 0x00000000). Software accessing RAM using the DMA engines must use bus addresses (based at 0xC0000000). 1.3 Peripheral access precautions for correct memory ordering The BCM2835 system uses an AMBA AXI-compatible interface structure. In order to keep the system complexity low and data throughput high, the BCM2835 AXI system does not always return read data in-order2. The GPU has special logic to cope with data arriving outof-order; however the ARM core does not contain such logic. Therefore some precautions must be taken when using the ARM to access peripherals. Accesses to the same peripheral will always arrive and return in-order. It is only when switching from one peripheral to another that data can arrive out-of-order. The simplest way to make sure that data is processed in-order is to place a memory barrier instruction at critical positions in the code. You should place: A memory write barrier before the first write to a peripheral. A memory read barrier after the last read of a peripheral. It is not required to put a memory barrier instruction after each read or write access. Only at those places in the code where it is possible that a peripheral read or write may be followed by a read or write of a different peripheral. This is normally at the entry and exit points of the peripheral service code. As interrupts can appear anywhere in the code so you should safeguard those. If an interrupt routine reads from a peripheral the routine should start with a memory read barrier. If an interrupt routine writes to a peripheral the routine should end with a memory write barrier. 2 Normally a processor assumes that if it executes two read operations the data will arrive in order. So a read from location X followed by a read from location Y should return the data of location X first, followed by the data of location Y. Data arriving out of order can have disastrous consequences. For example: a_status = *pointer_to_peripheral_a; b_status = *pointer_to_peripheral_b; Without precuations the values ending up in the variables a_status and b_status can be swapped around. It is theoretical possible for writes to go `wrong' but that is far more difficult to achieve. The AXI system makes sure the data always arrives in-order at its intended destination. So: *pointer_to_peripheral_a = value_a; *pointer_to_peripheral_b = value_b; will always give the expected result. The only time write data can arrive out-of-order is if two different peripherals are connected to the same external equipment. 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 7 2 Auxiliaries: UART1 & SPI1, SPI2
2.1 Overview The Device has three Auxiliary peripherals: One mini UART and two SPI masters. These three peripheral are grouped together as they share the same area in the peripheral register map and they share a common interrupt. Also all three are controlled by the auxiliary enable register. Auxiliary peripherals Register Map (offset = 0x7E21 5000) Address 0x7E21 5000 0x7E21 5004 0x7E21 5040 0x7E21 5044 0x7E21 5048 0x7E21 504C 0x7E21 5050 0x7E21 5054 0x7E21 5058 0x7E21 505C 0x7E21 5060 0x7E21 5064 0x7E21 5068 0x7E21 5080 0x7E21 5084 0x7E21 5088 0x7E21 5090 0x7E21 5094 0x7E21 50C0 0x7E21 50C4
3 Register Name3 AUX_IRQ AUX_ENABLES AUX_MU_IO_REG AUX_MU_IER_REG AUX_MU_IIR_REG AUX_MU_LCR_REG AUX_MU_MCR_REG AUX_MU_LSR_REG AUX_MU_MSR_REG AUX_MU_SCRATCH AUX_MU_CNTL_REG AUX_MU_STAT_REG AUX_MU_BAUD_REG Description Auxiliary Interrupt status Auxiliary enables Mini Uart I/O Data Mini Uart Interrupt Enable Size 3 3 8 8 Mini Uart Interrupt Identify 8...
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