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Unformatted text preview: rupt occurred on RX Read. Writing 1 to this bit clears it. Writing 0 has no effect. TX Write Interrupt Status / Clear This bit indicates an interrupt occurred on TX Write. Writing 1 to this bit clears it. Writing 0 has no effect. RW 0x0 2 TXERR RW 0x0 1 RXR RW 0x0 0 TXW RW 0x0 GRAY Register
Synopsis This register is used to control the gray mode generation. This is used to put the PCM into a special data/strobe mode. This mode is under 'best effort ' contract. Description Reserved - Write as 0, read as don't care RXFIFOLEVEL The Current level of the RXFIFO This indicates how many words are currently in the RXFIFO. The Number of bits that were flushed into the RXFIFO This indicates how many bits were valid when the flush operation was performed. The valid bits are from bit 0 upwards. Non-valid bits are set to zero. The Current fill level of the RX Buffer This indicates how many GRAY coded bits have been received. When 32 bits are received, they are written out into the RXFIFO. RO 0x0 Type Reset Bit(s) 31:22 21:16 Field Name 15:10 FLUSHED RO 0x0 9:4 RXLEVEL RO 0x0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 136 3 2 FLUSH Reserved - Write as 0, read as don't care Flush the RX Buffer into the RX FIFO This forces the RX Buffer to do an early write. This is necessary if we have reached the end of the message and we have bits left in the RX Buffer. Flushing will write these bits as a single 32 bit word, starting at bit zero. Empty bits will be packed with zeros. The number of bits written will be recorded in the FLUSHED Field. This bit is written as a 1 to initiate a flush. It will read back as a zero until the flush operation has completed (as the PCM Clock may be very slow). Clear the GRAY Mode Logic This Bit will reset all the GRAY mode logic, and flush the RX buffer. It is not self clearing. Enable GRAY Mode Setting this bit will put the PCM into GRAY mode. In gray mode the data is received on the data in and the frame sync pins. The data is expected to be in data/strobe format. RW 0x0 1 CLR RW 0x0 0 EN RW 0x0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 137 9 Pulse Width Modulator
9.1 Overview This section specifies in detail the functionality provided by the device Pulse Width Modulator (PWM) peripheral. The PWM controller incorporates the following features: Two independent output bit-streams, clocked at a fixed frequency. Bit-streams configured individually to output either PWM or a serialised version of a 32-bit word. PWM outputs have variable input and output resolutions. Serialise mode configured to load data to and/or read data from a FIFO storage block, which can store up to eight 32-bit words. Both modes clocked by clk_pwm which is nominally 100MHz, but can be varied by the clock manager. 9.2 Block Diagram 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 138 9.3 PWM Implementation A value represented as a ratio of N/M can be transmitted along a serial channel with pulse width modulation in which the value is represented by the duty cycle of the output signal. To send value N/M within a periodic sequence of M cycles, output should be 1 for N cycles and 0 for (M-N) cycles. The desired sequence should have 1's and 0's spread out as even as possible so that during any arbitrary period of time duty cycle achieves closest approximation of the value. This can be shown in the following table where 4/8 is modulated (N= 4, M= 8). Bad Fair Good 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 Sequence which gives the `good' approximation from the table above can be achieved by the following algorithm:
1. Set context = 0 2. context = context + N 3. if (context >= M) context = context M send 1 else where context is a register which stores the result of the addition/subtractions. 9.4 Modes of Operation PWM controller consists of two independent channels (pwm_chn in block diagram) which implement the pwm algorithm explained in section 1.3. Each channel can operate in either pwm mode or serialiser mode. PWM mode: There are two sub-modes in PWM mode: MSEN=0 and MSEN=1. When MSEN=0, which is the default mode, data to be sent is interpreted as the value N of the algorithm explained above. Number of clock cycles (range) used to send data is the value M of the algorithm. Pulses are sent within this range so that the resulting duty cycle is N/M. Channel sends its output continuously as long as data register is used, or buffer is used and it is not empty. 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 139 When MSEN=1, PWM block does not use the algorithm explained above, instead it sends serial data with the M/S ratio as in the picture below. M is the data to be sent, and S...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.
- Spring '13