Broadcom BCM2835

Word 2 destination address dma channel 5 cb word 3

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Unformatted text preview: 0x80c 0x810 0x814 0x81c 6_SOURCE_AD 6_DEST_AD 6_TXFR_LEN 6_STRIDE 6_NEXTCONBK 6_DEBUG 7_CS 7_CONBLK_AD 7_TI 7_SOURCE_AD 7_DEST_AD 7_TXFR_LEN 7_NEXTCONBK 7_DEBUG 8_CS 8_CONBLK_AD 8_TI 8_SOURCE_AD 8_DEST_AD 8_TXFR_LEN 8_NEXTCONBK DMA Channel 6 CB Word 1 (Source Address) DMA Channel 6 CB Word 2 (Destination Address) DMA Channel 6 CB Word 3 (Transfer Length) DMA Channel 6 CB Word 4 (2D Stride) DMA Channel 6 CB Word 5 (Next CB Address) DMA Channel 6 Debug DMA Channel 7 Control and Status DMA Channel 7 Control Block Address DMA Channel 7 CB Word 0 (Transfer Information) DMA Channel 7 CB Word 1 (Source Address) DMA Channel 7 CB Word 2 (Destination Address) DMA Channel 7 CB Word 3 (Transfer Length) DMA Channel 7 CB Word 5 (Next CB Address) DMA Channel 7 Debug DMA Channel 8 Control and Status DMA Channel 8 Control Block Address DMA Channel 8 CB Word 0 (Transfer Information) DMA Channel 8 CB Word 1 (Source Address) DMA Channel 8 CB Word 2 (Destination Address) DMA Channel 8 CB Word 3 (Transfer Length) DMA Channel 8 CB Word 5 (Next CB Address) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 44 0x820 0x900 0x904 0x908 0x90c 0x910 0x914 0x91c 0x920 0xa00 0xa04 0xa08 0xa0c 0xa10 0xa14 0xa1c 0xa20 0xb00 0xb04 0xb08 0xb0c 8_DEBUG 9_CS 9_CONBLK_AD 9_TI 9_SOURCE_AD 9_DEST_AD 9_TXFR_LEN 9_NEXTCONBK 9_DEBUG 10_CS 10_CONBLK_AD 10_TI 10_SOURCE_AD 10_DEST_AD 10_TXFR_LEN 10_NEXTCONBK 10_DEBUG 11_CS 11_CONBLK_AD 11_TI 11_SOURCE_AD DMA Channel 8 Debug DMA Channel 9 Control and Status DMA Channel 9 Control Block Address DMA Channel 9 CB Word 0 (Transfer Information) DMA Channel 9 CB Word 1 (Source Address) DMA Channel 9 CB Word 2 (Destination Address) DMA Channel 9 CB Word 3 (Transfer Length) DMA Channel 9 CB Word 5 (Next CB Address) DMA Channel 9 Debug DMA Channel 10 Control and Status DMA Channel 10 Control Block Address DMA Channel 10 CB Word 0 (Transfer Information) DMA Channel 10 CB Word 1 (Source Address) DMA Channel 10 CB Word 2 (Destination Address) DMA Channel 10 CB Word 3 (Transfer Length) DMA Channel 10 CB Word 5 (Next CB Address) DMA Channel 10 Debug DMA Channel 11 Control and Status DMA Channel 11 Control Block Address DMA Channel 11 CB Word 0 (Transfer Information) DMA Channel 11 CB Word 1 (Source Address) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 45 0xb10 0xb14 0xb1c 0xb20 0xc00 0xc04 0xc08 0xc0c 0xc10 0xc14 0xc1c 0xc20 0xd00 0xd04 0xd08 0xd0c 0xd10 0xd14 0xd1c 0xd20 0xe00 11_DEST_AD 11_TXFR_LEN 11_NEXTCONBK 11_DEBUG 12_CS 12_CONBLK_AD 12_TI 12_SOURCE_AD 12_DEST_AD 12_TXFR_LEN 12_NEXTCONBK 12_DEBUG 13_CS 13_CONBLK_AD 13_TI 13_SOURCE_AD 13_DEST_AD 13_TXFR_LEN 13_NEXTCONBK 13_DEBUG 14_CS DMA Channel 11 CB Word 2 (Destination Address) DMA Channel 11 CB Word 3 (Transfer Length) DMA Channel 11 CB Word 5 (Next CB Address) DMA Channel 11 Debug DMA Channel 12 Control and Status DMA Channel 12 Control Block Address DMA Channel 12 CB Word 0 (Transfer Information) DMA Channel 12 CB Word 1 (Source Address) DMA Channel 12 CB Word 2 (Destination Address) DMA Channel 12 CB Word 3 (Transfer Length) DMA Channel 12 CB Word 5 (Next CB Address) DMA Channel 12 Debug DMA Channel 13 Control and Status DMA Channel 13 Control Block Address DMA Channel 13 CB Word 0 (Transfer Information) DMA Channel 13 CB Word 1 (Source Address) DMA Channel 13 CB Word 2 (Destination Address) DMA Channel 13 CB Word 3 (Transfer Length) DMA Channel 13 CB Word 5 (Next CB Address) DMA Channel 13 Debug DMA Channel 14 Control and Status 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 46 0xe04 0xe08 0xe0c 0xe10 0xe14 0xe1c 0xe20 0xfe0 0xff0 14_CONBLK_AD 14_TI 14_SOURCE_AD 14_DEST_AD 14_TXFR_LEN 14_NEXTCONBK 14_DEBUG INT_STATUS ENABLE DMA Channel 14 Control Block Address DMA Channel 14 CB Word 0 (Transfer Information) DMA Channel 14 CB Word 1 (Source Address) DMA Channel 14 CB Word 2 (Destination Address) DMA Channel 14 CB Word 3 (Transfer Length) DMA Channel 14 CB Word 5 (Next CB Address) DMA Channel 14 Debug Interrupt status of each DMA channel Global enable bits for each DMA channel 32 32 32 32 32 32 32 32 32 0_CS 1_CS 2_CS 3_CS 4_CS 5_CS 6_CS 7_CS 8_CS 9_CS 10_CS 11_CS 12_CS 13_CS 14_CS Register Synopsis Bit(s) 31 DMA Control And Status register contains the main control and status bits for this DMA channel. Description DMA Channel Reset Writing a 1 to this bit will reset the DMA. The bit cannot be read, and will self clear. Abort DMA Writing a 1 to this bit will abort the current DMA CB. The DMA will load the next CB and attempt to continue. The bit cannot be read, and will self clear. Disable debug pause signal When set to 1, the DMA will not stop when the debug pause signal is asserted. Type W1SC Reset 0x0 Field Name RESET 30 ABORT W1SC 0x0 29 DISDEBUG RW 0x0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 47 28 WAIT_FOR_OUTST...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.

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