Unformatted text preview: nge of data can then proceed (where the first word in a data pair is for channel 1). This method should cause less disruption to the data stream. 8.6 PDM Input Mode Operation The PDM input mode is capable of interfacing with two digital half-cycle PDM microphones and implements a 4th order CIC decimation filter with a selectable decimation factor. The clock input of the microphones is shared with the PCM output codec and it should be configured to provide the correct clock rate for the microphones. As a result it may be necessary to add a number of padding bits into the PCM output and configure the output codec to allow for this. When using the PDM input mode the bit width and the rate of the data received will depend on the decimation factor used. Once the data has been read from the peripheral a further decimation and filtering stage will be required and can be implemented in software. The software filter should also correct the droop introduced by the CIC filter stage. Similarly a DC correction stage should also be employed.
0 (N=16) 1 (N=32) PCM_CLK (MHz) Peripheral Output Format
3.072 3.072 16 bits unsigned 20 bits unsigned OSR
4 2 Fs
48kHz 48kHz Table 8-1 PDM Input Mode Configuration 8.7 GRAY Code Input Mode Operation GRAY mode is used for an incoming data stream only. GRAY mode is selected by setting the enable bit (EN) in the PCM_GRAY register. In this mode data is received on the PCM_DIN (data) and the PCM_FS (strobe) pins. The data is expected to be in data/strobe format. In this mode data is detected when either the data or the strobe change state. As each bit is received it is written into the RX buffer and when 32 bits are received they are written out to the RXFIFO as a 32 bit word. In order for this mode to work the user must program a PCM clock rate which is 4 times faster then the gray data rate. Also the gray coded data input signals should be clean.
06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 124 The normal RXREQ and RXTHR FIFO levels will apply as for normal PCM received data. If a message is received that is not a multiple of 32 bits, any data in the RX Buffer can be flushed out by setting the flush bit (FLUSH). Once set, this bit will read back as zero until the flush operation has completed. This may take several cycles as the APB clock may be many times faster than the PCM clock. Once the flush has occurred, the bits are packed up to 32 bits with zeros and written out to the RXFIFO. The flushed field (FLUSHED) will indicate how many of bits of this word are valid. Note that to get an accurate indication of the number of bits currently in the rx shift register (RXLEVEL) the APB clock must be at least 2x the PCM_CLK. Figure 8-4 Gray mode input format 8.8 PCM Register Map There is only PCM module in the BCM2835. The PCM base address for the registers is 0x7E203000. PCM Address Map
Address Offset 0x0 0x4 0x8 0xc 0x10 0x14 Register Name CS_A FIFO_A MODE_A RXC_A TXC_A DREQ_A Description PCM Control and Status PCM FIFO Data PCM Mode PCM Receive Configuration PCM Transmit Configuration PCM DMA Request Level Size 32 32 32 32 32 32 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 125 0x18 0x1c 0x20 INTEN_A INTSTC_A GRAY PCM Interrupt Enables PCM Interrupt Status & Clear PCM Gray Mode Control 32 32 32 CS_A Register
Synopsis This register contains the main control and status bits for the PCM. The bottom 3 bits of this register can be written to whilst the PCM is running. The remaining bits cannot. Description Reserved - Write as 0, read as don't care STBY RAM Standby This bit is used to control the PCM Rams standby mode. By default this bit is 0 causing RAMs to start initially in standby mode. Rams should be released from standby prior to any transmit/receive operation. Allow for at least 4 PCM clock cycles to take effect. This may or may not be implemented, depending upon the RAM libraries being used. PCM Clock sync helper. This bit provides a software synchronisation mechanism to allow the software to detect when 2 PCM clocks have occurred. It takes 2 PCM clocks before the value written to this bit will be echoed back in the read value. RX Sign Extend 0 = No sign extension. 1 = Sign extend the RX data. When set, the MSB of the received data channel (as set by the CHxWID parameter) is repeated in all the higher data bits up to the full 32 bit data width. RX FIFO is Full 0 = RX FIFO can accept more data. 1 = RX FIFO is full and will overflow if more data is received. RW 0x0 Type Reset Bit(s) 31:26 25 Field Name 24 SYNC RW 0x0 23 RXSEX RW 0x0 22 RXF RO 0x0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 126 21 TXE TX FIFO is Empty 0 = TX FIFO is not empty. 1 = TX FIFO is empty and underflow will take place if no more data is written. Indicates that the RX FIFO contains data 0...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.
- Spring '13