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Unformatted text preview: not empty Channel 1 Mode 0: PWM mode 1: Serialiser mode Channel 1 Enable 0: Channel is disabled 1: Channel is enabled RW 0x0 9 MODE2 RW 0x0 8 PWEN2 RW 0x0 7 MSEN1 RW 0x0 6 CLRF1 RO 0x0 5 USEF1 RW 0x0 4 POLA1 RW 0x0 3 SBIT1 RW 0x0 2 RPTL1 RW 0x0 1 MODE1 RW 0x0 0 PWEN1 RW 0x0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 143 STA Register
Synopsis FULL1 bit indicates the full status of the FIFO. If this bit is high FIFO is full. EMPT1 bit indicates the empty status of the FIFO. If this bit is high FIFO is empty. WERR1 bit sets to high when a write when full error occurs. Software must clear this bit by writing 1. Writing 0 to this bit has no effect. RERR1 bit sets to high when a read when empty error occurs. Software must clear this bit by writing 1. Writing 0 to this bit has no effect. GAPOi. bit indicates that there has been a gap between transmission of two consecutive data from FIFO. This may happen when FIFO gets empty after state machine has sent a word and waits for the next. If control bit RPTLi is set to high this event will not occur. Software must clear this bit by writing 1. Writing 0 to this bit has no effect. BERR sets to high when an error has occurred while writing to registers via APB. This may happen if the bus tries to write successively to same set of registers faster than the synchroniser block can cope with. Multiple switching may occur and contaminate the data during synchronisation. Software should clear this bit by writing 1. Writing 0 to this bit has no effect. STAi bit indicates the current state of the channel which is useful for debugging purposes. 0 means the channel is not currently transmitting. 1 means channel is transmitting data. Description Reserved - Write as 0, read as don't care STA4 STA3 STA2 STA1 BERR GAPO4 GAPO3 GAPO2 GAPO1 RERR1 WERR1 Channel 4 State Channel 3 State Channel 2 State Channel 1 State Bus Error Flag Channel 4 Gap Occurred Flag Channel 3 Gap Occurred Flag Channel 2 Gap Occurred Flag Channel 1 Gap Occurred Flag Fifo Read Error Flag Fifo Write Error Flag RW RW RW RW RW RW RW RW RW RW RW 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Type Reset Bit(s) 31:13 12 11 10 9 8 7 6 5 4 3 2 Field Name 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 144 1 0 EMPT1 FULL1 Fifo Empty Flag Fifo Full Flag RW RW 0x1 0x0 DMAC Register
Synopsis ENAB bit is used to start DMA. PANIC bits are used to determine the threshold level for PANIC signal going active. Default value is 7. DREQ bits are used to determine the threshold level for DREQ signal going active. Default value is 7. Description DMA Enable 0: DMA disabled 1: DMA enabled Reserved - Write as 0, read as don't care PANIC DREQ DMA Threshold for PANIC signal DMA Threshold for DREQ signal RW RW 0x7 0x7 Type RW Reset 0x0 Bit(s) 31 Field Name ENAB 30:16 15:8 7:0 RNG1 Register
Synopsis This register is used to define the range for the corresponding channel. In PWM mode evenly distributed pulses are sent within a period of length defined by this register. In serial mode serialised data is transmitted within the same period. If the value in PWM_RNGi is less than 32, only the first PWM_RNGi bits are sent resulting in a truncation. If it is larger than 32 excess zero bits are padded at the end of data. Default value for this register is 32. Note: Channels 3 and 4 are not available in B0 and corresponding Channel Range Registers are ignored. Description Channel i Range Type RW Reset 0x20 Bit(s) 31:0 Field Name PWM_RNGi 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 145 DAT1 Register
Synopsis This register stores the 32 bit data to be sent by the PWM Controller when USEFi is 0. In PWM mode data is sent by pulse width modulation: the value of this register defines the number of pulses which is sent within the period defined by PWM_RNGi. In serialiser mode data stored in this register is serialised and transmitted. Note: Channels 3 and 4 are not available in B0 and corresponding Channel Data Registers are ignored. Description Channel i Data Type RW Reset 0x0 Bit(s) 31:0 Field Name PWM_DATi FIF1 Register
Synopsis This register is the FIFO input for the all channels. Data written to this address is stored in channel FIFO and if USEFi is enabled for the channel i it is used as data to be sent. This register is write only, and reading this register will always return bus default return value, pwm0 . When more than one channel is enabled for FIFO usage, the data written into the FIFO is shared between these channels in turn. For example if the word series A B C D E F G H I .. is written to FIFO and two channels are active and configured to use FIFO then channel 1 will transmit words A C E G I .. and channel 2 will transmit words B D F H .. . Note that requesting data from the FIFO is in locked-step manner and ther...
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- Spring '13