55 nspfcl 10 v qn to qn 1 5v 10 v 15 v tplh cp to q0

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Unformatted text preview: re calculated from the extrapolation formulas shown (CL in pF). HEF4020B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 6 of 14 HEF4020B NXP Semiconductors 14-stage binary counter Table 8. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf 20 ns; Tamb = 25 C. Symbol Parameter dynamic power dissipation PD Typical formula for PD (W) VDD where: PD = 600 fi + (fo CL) VDD 5V 2 fi = input frequency in MHz, 10 V PD = 2800 fi + (fo CL) VDD2 fo = output frequency in MHz, 15 V PD = 8200 fi + (fo CL) VDD CL = output load capacitance in pF, 2 VDD = supply voltage in V, (fo CL) = sum of the outputs. 11. Waveforms VI MR INPUT VM VSS tW trec VI CP INPUT 1/fmax VM VSS VOH Q0 or Qn OUTPUT VOL tPHL tPLH tW tPHL VM tt tt 001aae591 Measurement points are given in Table 9. Fig 7. Propagation delays, minimum pulse widths, transition and recovery times and maximum clock frequency Table 9. Measurement points Supply voltage Input Output VDD VM VM 5 V to 15 V 0.5VDD 0.5VDD HEF4020B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 7 of 14 HEF4020B NXP Semiconductors 14-stage binary counter tW VI 90 % 90 % negative pulse VM VM 10 % 0V 10 % tf tr VI tr tf 90 % positive pulse 90 % VM VM 10 % 0V 10 % tW 001aaj781 a. Input waveforms VDD VI VO G DUT CL RT 001aag182 b. Test circuit Test data is given in Table 10. Definitions for test circuit: DUT = Device Under Test. CL = load capacitance including jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig 8. Test circuit for measuring switching times Table 10. Test data Supply voltage Input VDD VI tr, tf CL 5 V to 15 V VSS or VDD 20 ns 50 pF HEF4020B Product data sheet Load All information provided in this document is subject to legal disclaimers. Rev. 8 — 18 November 2011 © NXP B.V. 2011. All rights reserved. 8 of 14 HEF4020B NXP Semiconductors 14-stage binary counter 12. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z wM b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30...
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This note was uploaded on 04/18/2013 for the course DIGITAL digital taught by Professor Ash during the Spring '13 term at Magnificat High School.

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