EE2731_Class_Notes_02-14

All gates are disabled forcing the bus voltage to be

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Unformatted text preview: VOHMin . Open Collector Devices Case when output voltage is VOLTyp . IR = IOLMax - 3IILMax RMin = VCC / IR Open Collector Devices Case when output voltage is VOHMin . IR = 4IOHMax + 3IIHMax RMax = (VCC - VOHMin ) / IR Select: RMin ≤ R ≤ RMax Transition Time Time interval between two reference points on a waveform. These reference points are usually 10% and 90% of the voltage change. Rise time( tr ) – Time interval when waveform is changing from a logic low to a logic high level. Fall time( tr ) – Time interval when waveform is changing from a logic high to a logic low level. Propagation Delay Time it takes for a change at the input of a device to produce a change at the output of the same. tpLH is the propagation delay when the output changes from LOW to HIGH. tpHL is the propagation delay when the output changes from HIGH to LOW. tpLH and tpHL are not necessarily equal, and their values depends on the logic family. Propagation Delay and Transition Time Fanout The number of gate inputs that a single output can drive or operate without exceeding its worst case loading specifications. IILMax is the maximum current supplied by an input when a LOW logic level voltage is applied to that input. IIHMax is the maximum current required by an input when a HIGH logic level voltage is applied to that input. IOLMax is the maximum current into an output when this output is in the LOW state. IOHMax is the maximum current provided by an output when this output is in the HIGH state. Fanout Fanout LS fanout = HS fanout = I OL I IL I OH I IH fanout = min{ LS fanout, HS fanout} Power Dissipation The power consumed by the gate that must be available from the power supply. This does not include the power delivered from another gate. VCC : supply voltage. ICCH : current drawn by the circuit when the output of the gate is HIGH. ICCL : current drawn by the circuit when the output of the gate is LOW. ICC : average current drawn by the circuit. PD : average power dissipation. Power Dissipation I CCH + I CCL I CC = 2 PD = VCC × I CC DC Noise Margins The maximum amount of voltage variation (noise) that may be permitted for LOW or HIGH voltage levels. VOHMin : the minimum output voltage in the HIGH state. VIHMin : the minimum input voltage guaranteed to be recognized as a HIGH. VILMax : the maximum input voltage guaranteed to be recognized as a LOW. VOLMax : the maximum output voltage in the LOW state. DC Noise Margins Low-State = VILMax – VOLMax High-State = VOHMin – VIHMin Unused Inputs Handle them as follows: Tie them to a used input in the same gate. Tie them to logic 1 through a pull-up resistor for AND & NAND gates. Tie them to logic 0 through a pull-down resistor for OR & NOR gates. Latches and Flip­Flops These sequential devices differ in the way their outputs are changed: The output of a latch changes independent of a clocking signal. The output of a flip–flop changes at specific times determined by a clocking signal. S­R Latch SR latch based on NOR gat...
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This note was uploaded on 04/28/2013 for the course EE 2731 taught by Professor Audiferred during the Spring '11 term at LSU.

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