EE2731_Class_Notes_02-14

The output of a flipflop changes at specific times

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Unformatted text preview: es. The S input sets the Q output to 1 while R reset it to 0. When R=S=0 then the output keeps the previous value. When R=S=1 then Q=Q’=0, and the latch may go to an unpredictable next state. S’­R’ Latch S’R’ latch based on NAND gates. The S’ input sets the Q output to 1 while R’ reset it to 0. When R’=S’=1 then the output keeps the previous value. When R’=S’=1 then Q=Q’=1, and the latch may go to an unpredictable next state. D Latch This latch eliminates the problem that occurs in the S’R’ latch when R=S=0. C is an enable input: When C=1 then the output follows the input D and the latch is said to be open. When C=0 then the output retains its last value and the latch is said to be closed. D Latch For proper operation the D input must not change during a time interval around the falling edge of C. This time interval is defined by the setup time – tsetup and the hold time – thold . Edge Triggered D Flip­Flop This flip-flop is made out of two D latches. The first latch is the master, and the second the slave. When Ck = 0 the master is open and the slave is closed. Qm and Ds follow Dm . When Ck = 1 the master is closed, the slave is open and Qm is transferred to Qs . Note that Qs does not change because the master latch is closed leaving Qm fixed. Edge Triggered D Flip­Flop The same constraints regarding setup and hold time discussed previously, also apply to the edge triggered D flip-flop. Edge Triggered J­K FlipFlop The operation of inputs J and K in the J-K flipflop is similar to the operation of inputs S and R in the S-R flip-flop. The difference arises when J and K are asserted simultaneously. In this situation the output of the J-K flip-flop inverts its current state. T Flip­Flop Also known as the toggle flip-flop. When input T = 0 the output Q retain its previous value. When input T = 1 the output Q inverts on every tick of the clock. When inputs J and K of a J-K flip-flop are connected together, the J-K flip-flop will behave like a T flip-flop. Logic Families Transistor Transistor Logic (TTL) is one of the most popular and widespread of all logic families. Very high number of SSI and MSI devices available in the market. Several number of sub-families that provide a wide range of speed and power consumption. Sub families: 74xx : The original TTL family. These devices had a propagation delay of 10ns and a power consumption of 10mW, and they were introduced in the early 60’s. Logic Families Sub families: 74Hxx : High speed. Speed was improved by reducing the internal resistors. Note that this improvement caused an increase in the power consumption. 74Lxx : Low power. Power consumption was improved by increasing the internal resistances, and the speed decreased. Logic Families Sub families: 74Sxx : Schottky. The use of Schottky transistors improved the speed. The power dissipation is less than the 74Hxx subfamily. 74LSxx : Low power Schottky. Uses Schottky transistors to improve speed. High internal resistances improves power consumption. Logic Families Sub f...
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This note was uploaded on 04/28/2013 for the course EE 2731 taught by Professor Audiferred during the Spring '11 term at LSU.

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