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circuit whose state
diagram contains a
single cycle. Modulus – number of
states in the cycle. Counters with nonpower of 2 modulus has
unused states Asynchronous Counters Ripple counter. Requires fewer
components than other
counters. Slowest one. Synchronous Counter Synchronous counters. The clock inputs of all flipflops in the counter
circuit are connected to a common clock signal. Synchronous Counter
Clock cycle
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Q2 changes Table 7.1. Derivation of the synchronous upcounter. Verilog Structural Representation Gate level primitives. Behavioral Representation Abstract expressions. Programming constructs. Verilog Syntax Logic circuit specification: module name (list of variables separated by commas); Verilog code endmodule input list of input variables separated by commas output list of output variables separated by commas Structural Representation Gate level primitives. Logic function (output variable, input variables
separated by commas) and (z1,x1,x2) or (z1,x1,x2,x3) nand (z1,x1,x2,x3,x4) nor (z1,x1,x2) not (z1,x1) Example 1 module example1 (x1, x2, x3, f); input x1, x2, x3; output f; and (g, x1, x2); x1
x2 not (k, x2); and (h, k, x3); or (f, g, h); endmodule f
x3 Verilog Syntax “~” is used to denote complementation. ~x1 = x1’ This simplifies the representation of the function
due to not having to use the “not” gate level
primitive. Example 1 module example1 (x1, x2, x3, f); input x1, x2, x3; output f; and (g, x1, x2); x1
x2 and (h, ~x2, x3); or (f, g, h); endmodule f
x3 Example 2 module example2 (x1, x2, x3, x4, f, g, h); input x1, x2, x3, x4; output f, g, h; and (z1, x1, x3); and (z2, x2, x4); or (g, z1, z2); or (z3, x1, ~x3); or (z4, ~x2, x4); and (h, z3, z4); or (f, g, h); Behavioral Representation Continuous assignment. Whenever a signal on the righthand side changes
states the lefthand side is
reevaluated. Assign keyword: Provides continuous assignment for a function. Assign f = (x1 & x2)  (~x2 & x3); The AND and OR operations are represented by the
“&” and “” signs. Example module example3 (x1, x2, x3, f); input x1, x2, x3; output f ; assign f = (x1 & x2)  (~x2 & x3); endmodule Example module example4 (x1, x2, x3, x4, f, g, h); input x1, x2, x3, x4; output f, g, h; assign g = (x1 & x3)  (x2 & x4); assign h = (x1  ~x3) & (~x2  x4); assign f = g  h; endmodule Ifelse Statement If (condition) Else Statements for condition being true
Statements for condition being false Example if(x2 == 1) f = x1; Else f = x3; Always Block Verilog syntax requires that procedural
statement be contained inside an “always block”. The block may contain a single statement or
multiple statements. The statements inside an always block are
evaluated sequentially in the order given in the
code. Always Block Syntax always @(sensitivity list) The sensitivity list indicates the signals used
inside the always block. The statement inside the always block are
executed whenever one or more signals in the
sensitivity list changes value. Reg Statement Verilog syntax requires that if a signal...
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This note was uploaded on 04/28/2013 for the course EE 2731 taught by Professor Audiferred during the Spring '11 term at LSU.
 Spring '11
 Audiferred

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