# Note you do not need to simplify your expression z 1 0

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Unformatted text preview: o the following multiplexer realization. (Note: You do not need to simplify your expression.) Z 1 0 Z’ 0 Z Z’ 1 I0 I1 I2 I3 I4 I5 I6 I7 O OUT S2 S1 S0 W X Y 3. Implement !"#\$(0,3,5,9,14,15) using an 8:1 mux. Assume you have the inverted versions of WXYZ if needed. 4. Draw the schematic for the following Verilog module module AOI (A, B, C, D, F); input A, B, C, D; output F; wire J, K, O; assign J = A & B; assign K = C & D; assign O = J | K; assign F = ~O; endmodule 5. Write a Verilog module called minority, it receives three inputs, a, b, and c. It produces one output, y, that is TRUE if at least two of the inputs are FALSE. 2...
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## This note was uploaded on 05/15/2013 for the course ECE 2300 taught by Professor Long during the Fall '08 term at Cornell.

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