05 - Week 5 8051 Addressing Modes 1 Addressing Mode The CPU...

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1 Week 5 8051 Addressing Modes
2 Addressing Mode The CPU can access data in various ways. The data could be in a register, or in memory; RAM or ROM, or be provided as an immediate value. These various ways of accessing data are called addressing modes . Five addressing modes in the 8051 1. immediate 2. register 3. direct 4. register indirect 5. indexed We use MOV as an example. One can use any instruction as long as that instruction supports the addressing mode.
3 Addressing modes 1. immediate: the operand is a constant MOV A,#1FH 2. register: the operand is in a register MOV A,R0 3. direct: access the data in the RAM with address MOV A,1FH 4. register indirect: the register holds the RAM address of the data MOV A,@R0 5. indexed: for on-chip ROM access MOVC A,@A+DPTR and external ROM/RAM access MOVX A,@DPTR
4 Immediate Addressing Mode The source operand is a constant. The immediate value can be loaded into any of the registers . The immediate data must be preceded by the pound sign, „# . The immediate value is bounded by the size of register. use the simulation tools to find the machine code and the content of registers after execution. See Tables 10 and 11 (page 614). When the instruction is assembled, the operand comes immediately after the opcode .
5 Examples Immediate Mode 1 0000 74 25 MOV A,#25H ;A=25H 2 0002 7C 3E MOV R4,#62 ;R4=62=3EH Instruction Opcodes in Table 11 Hex code Mnemonic Operands Byte 74 MOV A, #data 2 7C MOV R4, #data 2 Instruction Opcodes in Table 10 Mnemonic Oscillator Period MOV A, #data 12 MOV Rn, #data 12
6 More Immediate Mode 0004 90 45 21 MOV DPTR,#4521H Instruction Opcodes in Tables 10, 11 Hex code Mnemonic Operands Byte Oscillator Period 90 MOV DPTR, #data 3 24 DPTR =DPH+DPL equivalent to MOV DPL,#21H MOV DPH,#45H
7 Register addressing mode Register addressing mode involves the use of registers to hold the data . Register means Rn, A & CY. The source and destination registers must match in size. The movement of data between Rn registers is not allowed. “MOV R4,R7” is illegal. You can find that the opcode in register addressing mode is short
8 Example Register Mode 1 0000 E8 MOV A,R0 2 0001 FA MOV R2,A 3 0002 2D ADD A,R5 Instruction Opcodes in Table 11 Hex code Mnemonic Operands Byte E8 MOV A,R0 1 FA MOV R2,A 1 2D ADD A,R5 1
9 Direct addressing mode There are 128 bytes of RAM in the 8051. The RAM has been assigned address 00 - 7FH. 00-1FH: the register banks and stack 20-2FH: bit-addressable space to save single-bit data 30-7FH: scratch pad RAM There is no name for some RAM locations so we need to use direct address mode to access them; e.g., scratch pad RAM If a number begins without a pound sign, „# , then assembler thinks it as the RAM address. In direct addressing mode, the data is in a RAM memory location whose address is known, and this address is given as a part of the instruction. We can use the direct addressing mode to access 128-byte on chip RAM Special Function Registers (they have RAM addresses too.) MOV R0, 40H MOV 56H, A
10 Register banks If we use register bank 0, then the following

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