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Unformatted text preview: DD=2.5V and a minimum sized
inverter has input capacitance of 3fF.
Assume 1 billion transistor chip in 1.0 V 90nm process has 20% of logic transistors with an
average width of 10λ and 80% of memory transistors with average width of 4λ. Furthermore,
assume a gate capacitance of Cg = 2 fF/µm, an activity factor = 0.1 for Static CMOS logic gates
and an activity factor = 0.05 for memory arrays. Estimate dynamic power consumption per MHz.
Neglect wire capacitance and short-circuit current. Problem 3
The figure below shows two cases with waveforms “a” and “b” a...
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This note was uploaded on 06/01/2013 for the course AVLSI 6323 taught by Professor Bashir during the Spring '10 term at University of Florida.
- Spring '10