EEE6323S13-HW4

# EEE6323S13-HW4 - EEE6323 Advanced VLSI Design...

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EEE6323 Advanced VLSI Design Homework #4 (Due Thursday Feb 21, 2013) Qiuzhong Wu ( [email protected] ) Office Hours: Wed. 3:00pm-5:00pm Location: NEB 556 Homework submission: Hardcopy submission only (hand in homework to instructor at the beginning of class period on homework due date) Problem 1 Consider the following complex AOI gate. A B C D Y 14 35 a) Determine the boolean function for Y and implement the resulting logic using a compound gate (static CMOS logic). Remember to size the transistors for equal pull- down and pull-up resistances and to minimize the intrinsic delay (assume μ n =2μ p ). Input A should exhibit the same input capacitance as the complex gate above. Show all transistor sizes. b) Find the delay from A to Y (A Y) for your compound gate using logical effort. Show your work. c) Find the delay from A to Y (A Y) for the complex AOI gate above using logical effort. Which implementation is faster (compound gate or complex AOI gate)? Show your work.

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