IntelSoftwareDevelopersManual

1 7 reserved bits

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Unformatted text preview: 7-6 snooping mechanism . . . . . . . . . . . . . . . . . .7-8 write forwarding . . . . . . . . . . . . . . . . . . . . . .7-8 write ordering . . . . . . . . . . . . . . . . . . . . . . . .7-6 Memory type range registers (see MTRRs) Memory types caching methods, defined. . . . . . . . . . . . . . .9-5 choosing . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-8 MTRR types . . . . . . . . . . . . . . . . . . . . . . . .9-19 UC (uncacheable). . . . . . . . . . . . . . . . . . . . .9-5 WB (write back) . . . . . . . . . . . . . . . . . . . . . .9-6 WC (write combining) . . . . . . . . . . . . . . . . . .9-6 WP (write protected) . . . . . . . . . . . . . . . . . . .9-7 WT (write through) . . . . . . . . . . . . . . . . . . . .9-6 MemTypeGet() function . . . . . . . . . . . . . . . . . .9-28 MemTypeSet() function . . . . . . . . . . . . . . . . . .9-29 MESI cache protocol described . . . . . . . . . . . . . . . . . . . . . . . 9-4, 9-9 Mixing 16-bit and 32-bit code on Intel Architecture processors . . . . . . . .18-34 overview . . . . . . . . . . . . . . . . . . . . . . . . . . .17-1 MMX instructions pairing guidelines . . . . . . . . . . . . . . . . . . .14-17 Mode switching between real-address and protected mode 8-13 example . . . . . . . . . . . . . . . . . . . . . . . . . . .8-16 to SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-2 Model and stepping information, following processor initialization or reset . . . . .8-5 Model-specific registers (see MSRs) MOV instruction . . . . . . . . . . . . . . . . . . . . 3-9, 4-10 MOV (control registers) instructions. . . 2-20, 4-25, 7-12, 8-14 MOV (debug registers) instructions . . . 2-21, 4-25, 7-12, 15-10 MP (monitor coprocessor) flag, CR0 control register 2-16, 5-30, 8-6, 8-8 MP (monitor coprocessor) flag, CR0 register. .18-8 MSRs description of . . . . . . . . . . . . . . . . . . . . . . . .8-8 introduction of in Intel Architecture processors 18-38 introduction to . . . . . . . . . . . . . . . . . . . . . . . .2-5 machine-check architecture . . . . . . . . . . . .13-2 reading and writing . . . . . . . . . . . . . . . . . . .2-23 MTRR flag, EDX feature information register . 9-20 MTRRcap register . . . . . . . . . . . . . . . . . . . . . 9-20 MTRRdefType register . . . . . . . . . . . . . . . . . . 9-21 MTRRfix16K_80000 and MTRRfix16K_A0000 (fixed range) MTRRs . . . . . . . . . . . 9-23 MTRRfix4K_C0000. and MTRRfix4K_F8000 (fixed range) MTRRs . . . . . . . . . . . . . . . . 9-23 MTRRfix64K_00000 (fixed range) MTRR. . . . 9-22 MTRRphysBasen (variable range) MTRRs . . 9-23 MTRRphysMaskn (variable range) MTRRs . . 9-23 MTRRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 address mapping for fixed-range MTRRs . 9-23 cache control. . . . . . . . . . . . . . . . . . . . . . . 9-12 description of. . . . . . . . . . . . . . . . . . . .8-9, 9-18 enabling caching . . . . . . . . . . . . . . . . . . . . . 8-8 example of base and mask calculations . . 9-25 feature identification . . . . . . . . . . . . . . . . . 9-20 fixed-range registers . . . . . . . . . . . . . . . . . 9-22 initialization of . . . . . . . . . . . . . . . . . . . . . . 9-27 introduction of in Intel Architecture processors . . . . . . . . . . . . . . . . . . . . 18-39 large page size considerations . . . . . . . . . 9-32 mapping physical memory with . . . . . . . . . 9-20 memory types and their properties . . . . . . 9-19 MemTypeGet() function . . . . . . . . . . . . . . 9-28 MemTypeSet() function. . . . . . . . . . . . . . . 9-29 MTRRcap register . . . . . . . . . . . . . . . . . . . 9-20 MTRRdefType register . . . . . . . . . . . . . . . 9-21 multiple-processor considerations. . . . . . . 9-31 precedence of cache controls . . . . . . . . . . 9-13 precedences . . . . . . . . . . . . . . . . . . . . . . . 9-26 programming interface . . . . . . . . . . . . . . . 9-28 remapping memory types . . . . . . . . . . . . . 9-27 setting memory ranges . . . . . . . . . . . . . . . 9-21 state of following a hardware reset . . . . . . 9-18 variable-range registers . . . . . . . . . . . . . . 9-23 Multiple-processor initialization MP protocol . . . . . . . . . . . . . . . . . . . .7-45, 7-46 procedure . . . . . . . . . . . . . . . . . . . . . . . . . 7-48 Multiple-processor management bus locking . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 guaranteed atomic operations. . . . . . . . . . . 7-2 interprocessor and self-interrupts . . . . . . . 7-25 local APIC . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 memory ordering . . . . . . . . . . . . . . . . . . . . . 7-6 MP protocol . . . . . . . . . . . . . . . . . . . .7-45, 7-46 overview of . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 SMM considerations . . . . . . . . . . . . . . . . 12-17 Multiple-processor system MP protocol . . . . . . . . . . . . . . . . . . . .7-45, 7-46 relationship of local and I/O APICs . . . . . . 7-14 Multisegment model . . . . . . . . . . . . . . . . . . . . . 3-5 Multitasking initialization for . . . . . ....
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