IntelSoftwareDevelopersManual

13 4 first introduced

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Unformatted text preview: address translation . . . . . . . . . . . . . . 3-7 LDTR register description of. . . . . . . . . . . . . . . . . . .2-11, 3-18 introduction to . . . . . . . . . . . . . . . . . . . .2-3, 2-5 limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 storing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 LE (local exact breakpoint enable) flag, DR7 register . . . . . . . . . . . . .15-5 , 15-10 LEN0-LEN3 (Length) fields, DR7 register . . . 15-6 LES instruction . . . . . . . . . . . . . . . . 3-9, 4-10, 5-28 LFS instruction . . . . . . . . . . . . . . . . . . . . .3-9, 4-10 LGDT instruction. . . 2-20, 4-25, 7-12, 8-12, 18-25 LGS instruction . . . . . . . . . . . . . . . . . . . . .3-9, 4-10 LIDT instruction2-20, 4-25, 5-13, 7-12, 8-10, 16-6, 18-28 Limit checking description of. . . . . . . . . . . . . . . . . . . . . . . . 4-5 pointer offsets are within limits . . . . . . . . . 4-28 Limit field, segment descriptor . . . . . . . . . .4-2, 4-5 Linear address description of. . . . . . . . . . . . . . . . . . . . . . . . 3-6 introduction to . . . . . . . . . . . . . . . . . . . . . . . 2-5 Linear address space . . . . . . . . . . . . . . . . . . . . 3-6 defined . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 of task . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 Link (to previous task) field, TSS . . . . . . . . . . 5-19 Linking tasks mechanism . . . . . . . . . . . . . . . . . . . . . . . . 6-14 modifying task linkages . . . . . . . . . . . . . . . 6-16 LINT pins function of . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 programming . . . . . . . . . . . . . . . . . . . . . . . . E-1 LLDT instruction . . . . . . . . . . . . . . 2-20, 4-25, 7-12 LMSW instruction . . . . . . . . . . . . . . . . . .2-20, 4-25 Local APIC APIC_BASE_MSR . . . . . . . . . . . . . . . . . . 7-19 APR (arbitration priority register). . . . . . . . 7-32 arbitration priority . . . . . . . . . . . . . . . . . . . 7-22 block diagram . . . . . . . . . . . . . . . . . . . . . . 7-16 bus arbitration . . . . . . . . . . . . . . . . . . . . . . 7-15 cluster model. . . . . . . . . . . . . . . . . . . . . . . 7-21 current-count register . . . . . . . . . . . . . . . . 7-44 description of. . . . . . . . . . . . . . . . . . . . . . . 7-13 DFR (destination format register) . . . . . . . 7-21 divide configuration register . . . . . . . . . . . 7-43 enabling or disabling . . . . . . . . . . . . . . . . . 7-19 EOI (end-of-interrupt register) . . . . . . . . . . 7-33 ESR (error status register) . . . . . . . . . . . . 7-42 external interrupts . . . . . . . . . . . . . . . . . . . . 5-2 flat model. . . . . . . . . . . . . . . . . . . . . . . . . . 7-21 focus processor. . . . . . . . . . . . . . . . . . . . . 7-22 ID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20 identifying BSP . . . . . . . . . . . . . . . . . . . . . 7-19 indicating performance-monitoring counter overflow . . . . . . . . . . . . . . . . . . . . . . . 15-19 initial-count register . . . . . . . . . . . . . . . . . . 7-44 initialization . . . . . . . . . . . . . . . . . . . . . . . . 7-35 INDEX-9 INDEX interrupt acceptance . . . . . . . . . . . . . . . . . .7-30 interrupt acceptance decision flow chart. . .7-30 interrupt command register (ICR) . . . . . . . .7-25 interrupt destination . . . . . . . . . . . . . . . . . .7-20 interrupt distribution mechanism. . . . . . . . .7-22 interrupt sources . . . . . . . . . . . . . . . . . . . . .7-15 IRR (interrupt request register) . . . . . . . . . .7-30 ISR (in-service register) . . . . . . . . . . . . . . .7-30 LDR (logical destination register) . . . . . . . .7-20 local vector table (LVT). . . . . . . . . . . . . . . .7-23 logical destination mode . . . . . . . . . . . . . . .7-20 LVT (local-APIC version register) . . . . . . . .7-36 MDA (message destination address) . . . . .7-20 new features incorporated in the Pentium Pro processor. . . . . . . . . . . . . . . . . . . . . . . .7-45 physical destination mode . . . . . . . . . . . . .7-20 PPR (processor priority register) . . . . . . . .7-32 register address map . . . . . . . . . . . . . . . . .7-18 relationship of local APIC to I/O APIC . . . .7-14 relocating base address . . . . . . . . . . . . . . .7-19 serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2 SMI interrupt . . . . . . . . . . . . . . . . . . . . . . . .12-2 software visible differences between the local APIC on a Pentium Pro processor and the 82489DX . . . . . . . . . . . . . . . . . . . . . . . .7-44 spurious interrupt . . . . . . . . . . . . . . . . . . . .7-33 state after a software (INIT) reset . . . . . . . .7-35 state after INIT-deassert message . . . . . . .7-35 state after power-up reset. . . . . . . . . . . . . .7-35 state of . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-33 SVR (spurious-interrupt vector register) . . .7-34 timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-43 TMR (trigger mode register) . . . . . . . . . . . .7-30 TPR (task priority register) . . . . . . . . . . . . .7-31 valid interrupts . . . . . . . . . . . . . ....
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

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