IntelSoftwareDevelopersManual

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Unformatted text preview: . . . . . . . . . . . . . . . . . . . . 9-1 L1 (level 1) cache . . . . . . . . . . . . . . . . . . . . 9-2 L2 (level 2) cache . . . . . . . . . . . . . . . . . . . . 9-2 methods of caching available . . . . . . . . . . . 9-5 MTRRs, description of. . . . . . . . . . . . . . . . 9-18 operating modes . . . . . . . . . . . . . . . . . . . . 9-11 overview of . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 self-modifying code, effect on . . . . .9-15, 18-31 snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 TLBs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 UC (uncacheable) memory type . . . . . . . . . 9-5 WB (write back) memory type . . . . . . . . . . . 9-6 WC (write combining) memory type . . . . . . 9-6 WP (write protected) memory type . . . . . . . 9-7 write buffer . . . . . . . . . . . . . . . . . . . . .9-4, 9-17 write-back caching . . . . . . . . . . . . . . . . . . . 9-5 WT (write through) memory type. . . . . . . . . 9-6 Call gates 16-bit, interlevel return from . . . . . . . . . . 18-34 accessing a code segment through . . . . . 4-17 description of. . . . . . . . . . . . . . . . . . . . . . . 4-16 for 16-bit and 32-bit code modules . . . . . . 17-2 INDEX-2 INDEX introduction to . . . . . . . . . . . . . . . . . . . . . . . .2-3 mechanism . . . . . . . . . . . . . . . . . . . . . . . . .4-18 privilege level checking rules . . . . . . . . . . .4-19 CALL instruction. 3-9, 4-12, 4-13, 4-17, 4-23, 6-3, 6-10, 6-12, 17-7 Caller access privileges, checking . . . . . . . . . .4-28 Calls between 16- and 32-bit code segments . . .17-4 controlling the operand-size attribute for a call. . . . . . . . . . . . . . . . . . . . . . . . .17-7 returning from . . . . . . . . . . . . . . . . . . . . . . .4-23 CC0 and CC1 (counter control) fields, CESR MSR (Pentium processor). . . . . . . . . . . .15-20 CD (cache disable) flag, CR0 control register 2-13, 8-8, 9-9, 9-11, 9-13, 9-14, 9-31, 9-32, 18-22, 18-23, 18-30 CESR (control and event select) MSR (Pentium processor) . . . . . . . . . . . . . . . . . . .15-20 CLI instruction . . . . . . . . . . . . . . . . . . . . . . . . . .5-9 CLTS instruction. . . . . . . . . . . . . . . . . . . 2-20, 4-25 Cluster model, local APIC . . . . . . . . . . . . . . . .7-21 CMOVcc instructions . . . . . . . . . . . . . . . . . . . .18-3 CMPXCHG instruction . . . . . . . . . . . . . . . 7-4, 18-5 CMPXCHG8B instruction . . . . . . . . . . . . . 7-4, 18-4 Code modules 16 bit vs. 32 bit . . . . . . . . . . . . . . . . . . . . . .17-2 mixing 16-bit and 32-bit code . . . . . . . . . . .17-1 sharing data among mixed-size code segments. . . . . . . . . . . . . . . . . . . . . . . .17-3 transferring control among mixed-size code segments. . . . . . . . . . . . . . . . . . . . . . . .17-4 Code optimization 8/16 bit operands . . . . . . . . . . . . . . . . . . .14-33 accessing memory . . . . . . . . . . . . . . . . . .14-24 accessing memory, using MMX instructions . . . . . . . . . . . . . . . 14-24, 14-25 accessing memory, write allocation effects . . . . . . . . . . . . . . . . . . . . . . . . .14-27 address calculations . . . . . . . . . . . . . . . . .14-34 addressing modes and register usage . . .14-29 alignment, code . . . . . . . . . . . . . . . . . . . . .14-9 alignment, data . . . . . . . . . . . . . . . . . . . . . .14-9 alignment, data structures and arrays . . .14-10 alignment, dynamic allocation using malloc . . . . . . . . . . . . . . . . . . . . . . . . .14-11 alignment, memory and stack. . . . . . . . . .14-10 alignment, of static variables . . . . . . . . . .14-10 alignment, penalties . . . . . . . . . . . . . . . . . .14-9 alignment, rules and guidelines . . . . . . . . .14-9 alignment, using in-line assembly code . .14-11 branch prediction, eliminating and reducing number of branches . . . . . . . . . . . . . . .14-5 branch prediction, optimization . . . . . 14-4, 14-5 branch prediction, rules . . . . . . . . . . . . . . .14-4 clearing a register . . . . . . . . . . . . . . . . . . .14-34 compares with immediate zero . . . . . . . . .14-35 complex instructions . . . . . . . . . . . . . . . . .14-32 epilog sequence . . . . . . . . . . . . . . . . . . . .14-35 guidelines, floating-point code. . . . . . . . . . 14-2 guidelines, general . . . . . . . . . . . . . . . . . . 14-1 guidelines, MMX code. . . . . . . . . . . .14-2, 14-3 instruction length . . . . . . . . . . . . . . . . . . . 14-30 instruction pairing, general integer-instruction pairability rules. . . . . . . . . . . . . . . . . . 14-14 instruction pairing, general rules . . . . . . . 14-12 instruction pairing, guidelines . . . . . . . . . 14-12 instruction pairing, integer pairing rules . 14-13 instruction pairing, MMX instruction pairing guidelines. . . . . . . . . . . . . . . . . . . . . . 14-17 instruction pairing, pairing MMX and integer instructions. . . . . . . . . . . . . . . .14-17, 14-18 instruction pairing, pairing two MMX instructions. . . . . . . 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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

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