IntelSoftwareDevelopersManual

15 20 cd cache disable flag cr0 control

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Unformatted text preview: exception . . . . . . . . . . . . . . . . . . . . . . . . . .5-25 field recognition. . . . . . . . . . . . . . . . . . . . . .15-6 general-detect exception condition . . . . . .15-10 instruction breakpoint . . . . . . . . . . . . . . . . .15-7 instruction breakpoint exception condition .15-8 I/O breakpoint exception conditions . . . . . .15-9 LEN0 - LEN3 (Length) fields, DR7 register.15-6 R/W0-R/W3 (read/write) fields, DR7 register . . . . . . . . . . . . . . . . . . . . .15-6 single-step exception condition. . . . . . . . .15-10 task-switch exception condition . . . . . . . .15-11 BS (single step) flag, DR6 register. . . . . . . . . .15-5 BSP (bootstrap processor) flag, APIC_BASE_MSR . . . . . . . . . . . . . .7-19 BSWAP instruction. . . . . . . . . . . . . . . . . . . . . .18-5 BT (task switch) flag, DR6 register. . . . 15-5, 15-11 BTC instruction. . . . . . . . . . . . . . . . . . . . . . . . . .7-4 BTF (single-step on branches) flag, DebugCtlMSR register . . . . 15-12, 15-14 BTR instruction. . . . . . . . . . . . . . . . . . . . . . . . . .7-4 BTS instruction. . . . . . . . . . . . . . . . . . . . . . . . . .7-4 Built-in self-test (BIST) description of . . . . . . . . . . . . . . . . . . . . . . . .8-1 performing. . . . . . . . . . . . . . . . . . . . . . . . . . .8-2 Bus arbitration, APIC bus. . . . . . . . . . . . . . . . . .7-15 errors, detected with machine-check architecture . . . . . . . . . . . . . . . . . . . . .13-11 hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-37 locking. . . . . . . . . . . . . . . . . . . . . . . . 7-3, 18-37 Byte order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6 C C (conforming) flag, segment descriptor . . . . .4-13 C1 flag, FPU status word . . . . . . . . . . . 18-9 , 18-18 C2 flag, FPU status word . . . . . . . . . . . . . . . . .18-9 Cache control . . . . . . . . . . . . . . . . . . . . . . . . . .9-18 cache management instructions . . . . . . . . .9-15 cache mechanisms in Intel Architecture processors. . . . . . . . . . . . . . . . . . . . . .18-30 caching terminology . . . . . . . . . . . . . . . . . . .9-4 CD flag, CR0 control register . . . . . . 9-9, 18-23 choosing a memory type. . . . . . . . . . . . . . . .9-8 fixed-range MTRRs. . . . . . . . . . . . . . . . . . .9-22 flags and fields . . . . . . . . . . . . . . . . . . . . . . .9-9 flushing TLBs . . . . . . . . . . . . . . . . . . . . . . .9-17 G (global) flag, page-directory entries . . . 9-12, 9-17 G (global) flag, page-table entries . . 9-12, 9-17 internal caches . . . . . . . . . . . . . . . . . . . . . . .9-1 MemTypeGet() function . . . . . . . . . . . . . . .9-28 MemTypeSet() function . . . . . . . . . . . . . . .9-29 MESI protocol . . . . . . . . . . . . . . . . . . . . 9-4, 9-9 methods of caching available . . . . . . . . . . . .9-5 MTRR initialization . . . . . . . . . . . . . . . . . . .9-27 MTRR precedences . . . . . . . . . . . . . . . . . .9-26 MTRRs, description of . . . . . . . . . . . . . . . .9-18 multiple-processor considerations. . . . . . . 9-31 NW flag, CR0 control register . . . . .9-12, 18-23 operating modes . . . . . . . . . . . . . . . . . . . . 9-11 overview of . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 PCD flag, CR3 control register . . . . . . . . . 9-12 PCD flag, page-directory entries . . . 9-12, 9-13, 9-32 PCD flag, page-table entries . . 9-12, 9-13, 9-32 precedence of controls . . . . . . . . . . . . . . . 9-13 preventing caching . . . . . . . . . . . . . . . . . . 9-14 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 PWT flag, CR3 control register . . . . . . . . . 9-12 PWT flag, page-directory entries. . . .9-12, 9-32 PWT flag, page-table entries. . . . . . .9-12, 9-32 remapping memory types . . . . . . . . . . . . . 9-27 setting up memory ranges with MTRRs . . 9-21 variable-range MTRRs . . . . . . . . . . . . . . . 9-23 Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 cache hit . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 cache line . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 cache line fill . . . . . . . . . . . . . . . . . . . . . . . . 9-5 cache write hit . . . . . . . . . . . . . . . . . . . . . . . 9-5 description of. . . . . . . . . . . . . . . . . . . . . . . . 9-1 effects of a locked operation on internal processor caches. . . . . . . . . . . . . . . . . . 7-6 enabling. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 management, instructions . . . . . . . . . . . . . 2-21 Caching cache control protocol . . . . . . . . . . . . . . . . . 9-9 cache line . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 cache mechanisms in Intel Architecture processors . . . . . . . . . . . . . . . . . . . . . 18-30 caching terminology . . . . . . . . . . . . . . . . . . 9-4 choosing a memory type . . . . . . . . . . . . . . . 9-8 flushing TLBs . . . . . . . . . . . . . . . . . . . . . . 9-17 implicit caching . . . . . . . . . . . . . . . . . . . . . 9-16 internal caches . ....
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

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