IntelSoftwareDevelopersManual

15 7 last branch interrupt and exception recording

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Unformatted text preview: -17 instruction pairing, restrictions on pair execution 14-16 instruction pairing, special pairs . . . . . . . 14-16 instruction pairing, unpairability due to register dependencies . . . . . . . . . . . . 14-15 instruction scheduling, overview . . . . . . . 14-12 integer divide. . . . . . . . . . . . . . . . . . . . . . 14-34 integer instruction selection and optimizations . . . . . . . . . . . . . . . . . . . 14-32 LEA instruction . . . . . . . . . . . . . . . . . . . . 14-32 partial register stalls, reducing . . . . . . . . . 14-7 pipelining, floating-point instructions . . . . 14-18 pipelining, floating-point operations with integer operands . . . . . . . . . . . . . . . . . . . . . . 14-21 pipelining, FSTSW instruction . . . . . . . . . 14-21 pipelining, FXCH guidelines . . . . . . . . . . 14-22 pipelining, guidelines. . . . . . . . . . . . . . . . 14-18 pipelining, hiding the one-clock latency of a floating-point store . . . . . . . . . . . . . . . 14-20 pipelining, integer and floating-point multiply. . . . . . . . . . . . . . . . . . . . . . . . 14-21 pipelining, MMX instructions . . . . . . . . . . 14-18 pipelining, pairing of floating-point instructions. . . . . . . . . . . . . . . . . . . . . 14-19 pipelining, transcendental instructions . . 14-22 pipelining, using integer instructions to hide latencies and schedule floating-point instructions. . . . . . . . . . . . . . . . . . . . . 14-19 prefixed opcodes. . . . . . . . . . . . . . . . . . . 14-31 prolog sequences . . . . . . . . . . . . . . . . . . 14-34 PUSH mem instruction . . . . . . . . . . . . . . 14-33 scheduling, rules for Pentium II and Pentium Pro processors . . . . . . . . . . . . . . . . . . . . . 14-22 short opcodes . . . . . . . . . . . . . . . . . . . . . 14-33 zero-extension of short integers . . . . . . . 14-32 Code optimizations compares . . . . . . . . . . . . . . . . . . . . . . . . 14-34 Code segments accessing data in . . . . . . . . . . . . . . . . . . . 4-12 accessing through a call gate . . . . . . . . . . 4-17 description of. . . . . . . . . . . . . . . . . . . . . . . 3-13 descriptor format . . . . . . . . . . . . . . . . . . . . . 4-3 descriptor layout . . . . . . . . . . . . . . . . . . . . . 4-3 INDEX-3 INDEX direct calls or jumps to . . . . . . . . . . . . . . . .4-13 executable (defined) . . . . . . . . . . . . . . . . . .3-12 pointer size . . . . . . . . . . . . . . . . . . . . . . . . .17-5 privilege level checking when transferring program control between code segments. . . . . . . . . . . . . . . . . . . . . . . .4-12 Compatibility Intel Architecture. . . . . . . . . . . . . . . . . . . . .18-1 software . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6 Condition code flags, FPU status word compatibility information . . . . . . . . . . . . . . .18-8 Conforming code segments accessing . . . . . . . . . . . . . . . . . . . . . . . . . .4-15 C (conforming) flag . . . . . . . . . . . . . . . . . . .4-13 description of . . . . . . . . . . . . . . . . . . . . . . .3-14 Context, task (see Task state) Control registers CR0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-12 CR1 (reserved) . . . . . . . . . . . . . . . . . . . . . .2-12 CR2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-12 CR3 (PDBR) . . . . . . . . . . . . . . . . . . . . 2-5, 2-12 CR4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-12 description of . . . . . . . . . . . . . . . . . . . . . . .2-12 introduction to . . . . . . . . . . . . . . . . . . . . . . . .2-5 qualification of flags with CPUID instruction . . . . . . . . . . . . . . . . . . . . . . .2-18 Coprocessor segment overrun exception . . . 5-34, 18-14 Counter mask field, PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family processors) . . . .15-17 CPL description of . . . . . . . . . . . . . . . . . . . . . . . .4-8 field, CS segment selector . . . . . . . . . . . . . .4-3 CPUID instruction. . 2-18, 7-12, 9-20, 13-7, 15-14, 15-19, 18-2, 18-4, 18-38 CR0 control register . . . . . . . . . . . . . . . . . . . . .18-8 description of . . . . . . . . . . . . . . . . . . . . . . .2-12 introduction to . . . . . . . . . . . . . . . . . . . . . . . .2-5 state following processor reset . . . . . . . . . . .8-2 CR1 control register (reserved) . . . . . . . . . . . .2-12 CR2 control register description of . . . . . . . . . . . . . . . . . . . . . . .2-12 introduction to . . . . . . . . . . . . . . . . . . . . . . . .2-5 CR3 control register (PDBR) associated with a task. . . . . . . . . . . . . . 6-1, 6-3 description of . . . . . . . . . . . . . . . . . . 2-12, 3-23 in TSS . . . . . . . . . . . . . . . . . . . . . . . . . 6-6, 6-17 introduction to . . . . . . . . . . . . . . . . . . . . . . . .2-5 loading during initialization . . . . . . . . . . . . .8-13 memory management. . . . . . . . . . . . . . . . . .2-5 CR4 control register . . . . . . . . . . . . . . . . . . . . .18-2 description of . . . . . . . . . . . . . . . . . . . . . . .2-12 inclusion in Intel A...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

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