IntelSoftwareDevelopersManual

16 14 instruction restart flag

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Unformatted text preview: 11 real-address mode . . . . . . . . . . . . . . . . . . 8-10 RESET# pin . . . . . . . . . . . . . . . . . . . . . . . . 8-1 setting up exception- and interrupt-handling facilities . . . . . . . . . . . . . . . . . . . . . . . . 8-12 INIT# pin . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2, 8-2 INIT# signal . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 INS instruction . . . . . . . . . . . . . . . . . . . . . . . 15-10 Instruction operands . . . . . . . . . . . . . . . . . . . . . 1-7 Instruction set new instructions . . . . . . . . . . . . . . . . . . . . 18-3 obsolete instructions . . . . . . . . . . . . . . . . . 18-5 Instruction-breakpoint exception condition . . . 15-8 Instructions privileged. . . . . . . . . . . . . . . . . . . . . . . . . . 4-25 serializing . . . . . . . . . . . . . . . . . . . . . . . . 18-19 supported in real-address mode . . . . . . . . 16-4 system. . . . . . . . . . . . . . . . . . . . . . . . .2-6, 2-18 INT 3 instruction . . . . . . . . . . . . . . . . . . .5-25, 15-2 INT instruction . . . . . . . . . . . . . . . . . . . . . . . . 4-12 INT n instruction . . . . . . . . . . . . . . . . . 3-9, 5-1, 5-3 INDEX-7 INT (APIC interrupt enable) flag, PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family processors) 15-17 INT3 instruction . . . . . . . . . . . . . . . . . . . . . 3-9, 5-3 Intel 287 math coprocessor . . . . . . . . . . . . . . .18-7 Intel 387 math coprocessor system . . . . . . . . .18-7 Intel 487 SX math coprocessor . . . . . . 18-7, 18-20 Intel 8086 processor. . . . . . . . . . . . . . . . . . . . .18-7 Intel Architecture compatibility . . . . . . . . . . . . . . . . . . . . . . . .18-1 processors . . . . . . . . . . . . . . . . . . . . . . . . .18-1 Intel286 processor . . . . . . . . . . . . . . . . . . . . . .18-7 Intel386 DX processor . . . . . . . . . . . . . . . . . . .18-7 Intel486 DX processor . . . . . . . . . . . . . . . . . . .18-7 Intel486 SX processor . . . . . . . . . . . . . 18-7, 18-20 Interprivilege level calls call mechanism . . . . . . . . . . . . . . . . . . . . . .4-17 stack switching . . . . . . . . . . . . . . . . . . . . . .4-21 Interrupt command register (ICR), local APIC .7-25 Interrupt gates 16-bit, interlevel return from . . . . . . . . . . .18-34 clearing IF flag . . . . . . . . . . . . . . . . . . 5-9, 5-18 difference between interrupt and trap gates . . 5-18 for 16-bit and 32-bit code modules . . . . . . .17-2 handling a virtual-8086 mode interrupt or exception through . . . . . . . . . . . . . . . .16-17 in IDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-13 introduction to . . . . . . . . . . . . . . . . . . . . 2-3, 2-4 layout of . . . . . . . . . . . . . . . . . . . . . . . . . . .5-13 Interrupt handler calling . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-15 defined . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1 flag usage by handler procedure . . . . . . . .5-18 procedures . . . . . . . . . . . . . . . . . . . . . . . . .5-15 protection of handler procedures . . . . . . . .5-17 task . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18, 6-3 Interrupt redirection bit map field (in TSS) . . .16-16 Interrupts acceptance, local APIC. . . . . . . . . . . . . . . .7-30 APIC priority levels . . . . . . . . . . . . . . . . . . .7-15 automatic bus locking when acknowledging. . . . . . . . . . . . . . . . . . .18-37 control transfers between 16- and 32-bit code modules. . . . . . . . . . . . . . . . . . . . . . . . .17-8 description of . . . . . . . . . . . . . . . . . . . . 2-4, 5-1 distribution mechanism, local APIC . . . . . .7-22 enabling and disabling . . . . . . . . . . . . . . . . .5-8 handler mechanism . . . . . . . . . . . . . . . . . .5-15 handler procedures. . . . . . . . . . . . . . . . . . .5-15 handling . . . . . . . . . . . . . . . . . . . . . . . . . . .5-15 handling in real-address mode . . . . . . . . . .16-6 handling in SMM . . . . . . . . . . . . . . . . . . . .12-10 handling in virtual-8086 mode. . . . . . . . . .16-15 handling multiple NMIs . . . . . . . . . . . . . . . . .5-8 handling through a task gate in virtual-8086 mode . . . . . . . . . . . . . . . . . . . . . . . . . .16-20 handling through a trap or interrupt gate in virtual-8086 mode . . . . . . . . . . . . . . . 16-17 IDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 IDTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 initializing for protected-mode operation . . 8-12 interrupt descriptor table register (see IDTR) interrupt descriptor table (see IDT) local APIC . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 local APIC sources . . . . . . . . . . . . . . . . . . 7-15 maskable hardware interrupts. . . . . . .2-8, 7-23 masking maskable hardware interrupts . . . 5-8 masking when switching stack segments . 5-10 overview of . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 priorities among simultaneous exceptions and interrupts . . . . . . . . . . . . . . . . . . . . . . . 5-10 propagation delay...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

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