IntelSoftwareDevelopersManual

16 8 software interrupt

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Unformatted text preview: . . . . . . . . . . . . . . . . . . . . . . . .15-8 Real-Address Mode Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . . . .16-8 Software Interrupt Handling Methods While in Virtual-8086 Mode . . . . . . . .16-24 Characteristics of 16-Bit and 32-Bit Program Modules. . . . . . . . . . . . . . . . . .17-1 New Instructions in the Pentium® and Later Intel Architecture Processors . .18-3 Recommended Values of the FP Related Bits for Intel486™ SX Microprocessor/Intel 487 SX Math Coprocessor System . . . . . . . . . . . . . . .18-20 EM and MP Flag Interpretation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-20 Events That Can Be Counted with the P6 Family PerformanceMonitoring Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 Events That Can Be Counted with the Pentium® Processor PerformanceMonitoring Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-12 Model-Specific Registers (MSRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 xxii 1 About This Manual CHAPTER 1 ABOUT THIS MANUAL The Intel Architecture Software Developer’s Manual, Volume 2: Instruction Set Reference (Order Number 243191) is part of a three-volume set that describes the architecture and programming environment of all Intel Architecture processors. The other two volumes in this set are: • • The Intel Architecture Software Developer’s Manual, Volume 1: Basic Architecture (Order Number 243190). The Intel Architecture Software Developer’s Manual, Volume 3: System Programing Guide (Order Number 243192). The Intel Architecture Software Developer’s Manual, Volume 1, describes the basic architecture and programming environment of an Intel Architecture processor; the Intel Architecture Software Developer’s Manual, Volume 2, describes the instructions set of the processor and the opcode structure. These two volumes are aimed at application programmers who are writing programs to run under existing operating systems or executives. The Intel Architecture Software Developer’s Manual, Volume 3, describes the operating-system support environment of an Intel Architecture processor, including memory management, protection, task management, interrupt and exception handling, and system management mode. It also provides Intel Architecture processor compatibility information. This volume is aimed at operating-system and BIOS designers and programmers. 1.1. P6 FAMILY PROCESSOR TERMINOLOGY This manual includes information pertaining primarily to the 32-bit Intel Architecture processors, which include the Intel386™, Intel486™, and Pentium® processors, and the P6 family processors. The P6 family processors are those Intel Architecture processors based on the P6 family microarchitecture. This family includes the Pentium® Pro, Pentium® II, Pentium® III processor, and any future processors based on the P6 family microarchitecture. 1.2. OVERVIEW OF THE INTEL ARCHITECTURE SOFTWARE DEVELOPER’S MANUAL, VOLUME 3: SYSTEM PROGRAMMING GUIDE The contents of this manual are as follows: Chapter 1 — About This Manual. Gives an overview of all three volumes of the Intel Architecture Software Developer’s Manual. It also describes the notational conventions in these manuals and lists related Intel manuals and documentation of interest to programmers and hardware designers. 1-1 ABOUT THIS MANUAL Chapter 2 — System Architecture Overview. Describes the modes of operation of an Intel Architecture processor and the mechanisms provided in the Intel Architecture to support operating systems and executives, including the system-oriented registers and data structures and the system-oriented instructions. The steps necessary for switching between real-address and protected modes are also identified. Chapter 3 — Protected-Mode Memory Management. Describes the data structures, registers, and instructions that support segmentation and paging and explains how they can be used to implement a “flat” (unsegmented) memory model or a segmented memory model. Chapter 4 — Protection. Describes the support for page and segment protection provided in the Intel Architecture. This chapter also explains the implementation of privilege rules, stack switching, pointer validation, user and supervisor modes. Chapter 5 — Interrupt and Exception Handling. Describes the basic interrupt mechanisms defined in the Intel Architecture, shows how interrupts and exceptions relate to protection, and describes how the architecture handles each exception type. Reference information for each Intel Architecture exception is given at the end of this chapter. Chapter 6 — Task Management. Describes the mechanisms the Intel Architecture provides to support multitasking and inter-task protection. Chapter 7 — Multiple-Processor Management. Describes the instructions and flags that support multiple processors with shared memory, memory ordering, and the advanced programmable interrupt controller (APIC). Chapter 8 — Processor...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

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