IntelSoftwareDevelopersManual

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Unformatted text preview: rchitecture . . . . . . . . . .18-21 introduction to . . . . . . . . . . . . . . . . . . . . . . . .2-5 CS register . . . . . . . . . . . . . . . . . . . . . . . . . . .18-12 saving on call to exception or interrupt handler . . . . . . . . . . . . . . . . . . . . . . . . .5-15 state following initialization . . . . . . . . . . . . . .8-6 CS segment selector, CPL field . . . . . . . . . . . . 4-3 CTR0 and CTR1 (performance counters) MSRs (Pentium processor) . . . . . .15-20, 15-22 Current privilege level (see CPL) Current-count register, local APIC . . . . . . . . . 7-44 D D (default operation size) flag, segment descriptor. . . . . . . .17-2, 18-34 D (dirty) flag, page-table entry . . . . . . . . . . . . 3-27 Data breakpoint exception conditions. . . . . . . 15-9 Data segments description of. . . . . . . . . . . . . . . . . . . . . . . 3-13 descriptor layout . . . . . . . . . . . . . . . . . . . . . 4-3 expand-down type. . . . . . . . . . . . . . . . . . . 3-12 privilege level checking when accessing. . . 4-9 DB0-DB3 breakpoint-address registers . . . . . 15-1 DB6 debug status register . . . . . . . . . . . . . . . 15-1 DB7 debug control register. . . . . . . . . . . . . . . 15-1 DE (debugging extensions) flag, CR4 control register . . . . . 2-17, 18-22, 18-24, 18-25 DE (denormal operand exception) flag, FPU status word . . . . . . . . . . . . .11-17, 11-19 Debug exception (#DB) 5-9, 5-23, 6-6, 15-1, 15-8, 15-13 Debug registers description of. . . . . . . . . . . . . . . . . . . . . . . 15-2 introduction to . . . . . . . . . . . . . . . . . . . . . . . 2-5 loading. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 DebugCtlMSR register . . . . . . . . . . . . .15-1, 15-11 Debugging facilities debug registers . . . . . . . . . . . . . . . . . . . . . 15-2 exceptions . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 last branch, interrupt, and exception recording . . . . . . . . . . . . . . . . . . . . . . 15-11 masking debug exceptions . . . . . . . . . . . . . 5-9 overview of . . . . . . . . . . . . . . . . . . . . . . . . 15-1 performance-monitoring counters . . . . . . 15-15 time-stamp counter . . . . . . . . . . . . . . . . . 15-14 DEC instruction. . . . . . . . . . . . . . . . . . . . . . . . . 7-4 Denormal operand exception (#D) . . .11-19, 18-11 Denormalized operand . . . . . . . . . . . . . . . . . 18-15 Device-not-available exception (#NM) . . 5-30, 8-8, 18-13, 18-14 DFR (destination format register), local APIC 7-21 DIV instruction . . . . . . . . . . . . . . . . . . . . . . . . 5-22 Divide configuration register, local APIC . . . . 7-43 Divide-error exception (#DE) . . . . . . . .5-22, 18-26 Division-by-zero exception (#Z) . . . . . . . . . . 11-18 Double-fault exception (#DF) . . . . . . . .5-32, 18-28 DPL (descriptor privilege level) field, segment descriptor . . . . . . . . . . . . . 3-12, 4-2, 4-8 DR0-DR3 breakpoint-address registers . . . . . 15-4, 15-12, 15-13 DR4-DR5 debug registers . . . . . . . . . .15-4, 18-25 DR6 debug status register . . . . . . . . . . . . . . . 15-4 INDEX-4 INDEX B0-B3 (breakpoint condition detected) flags. . . . . . . . . . . . . . . . . . . . . . . . . . . .15-4 BD (debug register access detected) flag. .15-4 BS (single step) flag . . . . . . . . . . . . . . . . . .15-5 BT (task switch) flag . . . . . . . . . . . . . . . . . .15-5 debug exception (#DB) . . . . . . . . . . . . . . . .5-23 reserved bits . . . . . . . . . . . . . . . . . . . . . . .18-24 DR7 debug control register . . . . . . . . . . . . . . .15-5 G0-G3 (global breakpoint enable) flags . . .15-5 GD (general detect enable) flag . . . . . . . . .15-5 GE (global exact breakpoint enable) flag . .15-5 L0-L3 (local breakpoint enable) flags . . . . .15-5 LE local exact breakpoint enable) flag . . . .15-5 LEN0-LEN3 (Length) fields. . . . . . . . . . . . .15-6 R/W0-R/W3 (read/write) fields . . . . 15-6, 18-24 D/B (default operation size/default stack pointer size and/or upper bound) flag, segment descriptor . . . . . . . . . . . . . . . . . 3-12, 4-5 E E (edge detect) flag, PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family processors) . . . .15-17 E (enable/disable APIC) flag, APIC_BASE_MSR . . . . . . . . . . . . . .7-19 E (expansion direction) flag, segment descriptor . . . . . . . . . . . . . . . . . . 4-2, 4-5 E (MTRRs enabled) flag, MTRRdefType register . . . . . . . . . . . . . . . . . . 7-19, 9-22 EFLAGS register introduction to . . . . . . . . . . . . . . . . . . . . . . . .2-5 new flags. . . . . . . . . . . . . . . . . . . . . . . . . . .18-6 saved in TSS . . . . . . . . . . . . . . . . . . . . . . . .6-4 saving on call to exception or interrupt handler . . . . . . . . . . . . . . . . . . . . . . . . .5-15 using flags to distinguish between 32-bit Intel Architecture processors. . . . . . . . . . . . .18-6 EIP register . . . . . . . . . . . . . . . . . . . . . . . . . .18-12 saved in TSS . . . . . . . . . . . . . . . . . . . . . . . .6-4 saving on call to exception or interrupt handler . . . . . . . . . . . . . . . . . . . . . . . . .5-15 state following initia...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

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