IntelSoftwareDevelopersManual

18 38 intel architecture compatibility 18313 memory

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Unformatted text preview: ction is executed. No reads (as a result of cache miss) are reordered around previously generated writes sitting in the write buffers. The implication of this is that the write buffers will be flushed or emptied before a subsequent bus cycle is run on the external bus. On both the Intel486™ and Pentium® processors, under certain conditions, a memory read will go onto the external bus before the pending memory writes in the buffer even though the writes occurred earlier in the program execution. A memory read will only be reordered in front of all writes pending in the buffers if all writes pending in the buffers are cache hits and the read is a cache miss. Under these conditions, the Intel486™ and Pentium® processors will not read from an external memory location that needs to be updated by one of the pending writes. During a locked bus cycle, the Intel486™ processor will always access external memory, it will never look for the location in the on-chip cache. All data pending in the Intel486™ processor's write buffers will be written to memory before a locked cycle is allowed to proceed to the external bus. Thus, the locked bus cycle can be used for eliminating the possibility of reordering read cycles on the Intel486™ processor. The Pentium® processor does check its cache on a read- 18-36 INTEL ARCHITECTURE COMPATIBILITY modify-write access and, if the cache line has been modified, writes the contents back to memory before locking the bus. The P6 family processors write to their cache on a read-modifywrite operation (if the access does not split across a cache line) and does not write back to system memory. If the access does split across a cache line, it locks the bus and accesses system memory. I/O reads are never reordered in front of buffered memory writes on an Intel Architecture processor. This ensures an update of all memory locations before reading the status from an I/O device. 18.28. BUS LOCKING The Intel 286 processor performs the bus locking differently than the Intel P6 family, Pentium®, Intel486™, and Intel386™ processors. Programs that use forms of memory locking specific to the Intel 286 processor may not run properly when run on later processors. A locked instruction is guaranteed to lock only the area of memory defined by the destination operand, but may lock a larger memory area. For example, typical 8086 and Intel 286 configurations lock the entire physical memory space. Programmers should not depend on this. On the Intel 286 processor, the LOCK prefix is sensitive to IOPL. If the CPL is greater than the IOPL, a general-protection exception (#GP) is generated. On the Intel386™ DX, Intel486™, and Pentium®, and P6 family processors, no check against IOPL is performed. The Pentium® processor automatically asserts the LOCK# signal when acknowledging external interrupts. After signaling an interrupt request, an external interrupt controller may use the data bus to send the interrupt vector to the processor. After receiving the interrupt request signal, the processor asserts LOCK# to insure that no other data appears on the data bus until the interrupt vector is received. This bus locking does not occur on the P6 family processors. 18.29. BUS HOLD Unlike the 8086 and Intel 286 processors, but like the Intel386™ and Intel486™ processors, the P6 family and Pentium® processors respond to requests for control of the bus from other potential bus masters, such as DMA controllers, between transfers of parts of an unaligned operand, such as two words which form a doubleword. Unlike the Intel386™ processor, the P6 family, Pentium® and Intel486™ processors respond to bus hold during reset initialization. 18.30. TWO WAYS TO RUN INTEL 286 PROCESSOR TASKS When porting 16-bit programs to run on 32-bit Intel Architecture processors, there are two approaches to consider: • Porting an entire 16-bit software system to a 32-bit processor, complete with the old operating system, loader, and system builder. Here, all tasks will have 16-bit TSSs. The 32bit processor is being used as if it were a faster version of the 16-bit processor. 18-37 INTEL ARCHITECTURE COMPATIBILITY • Porting selected 16-bit applications to run in a 32-bit processor environment with a 32-bit operating system, loader, and system builder. Here, the TSSs used to represent 286 tasks should be changed to 32-bit TSSs. It is possible to mix 16 and 32-bit TSSs, but the benefits are small and the problems are great. All tasks in a 32-bit software system should have 32bit TSSs. It is not necessary to change the 16-bit object modules themselves; TSSs are usually constructed by the operating system, by the loader, or by the system builder. Refer to Chapter 17, Mixing 16-Bit and 32-Bit Code for more detailed information about mixing 16-bit and 32-bit code. Because the 32-bit processors use the contents of the reserved word of 16-bit segment descriptors, 16-bit programs that place values in this word may not run correctly on the 32-bit processors. 18.31. MODEL-SPECIFIC EXTENSIONS TO THE INTEL ARCHITECTURE Certain extensions to the Intel Architecture are specific to a processor or family of Intel Architecture processors and may not be implement...
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