IntelSoftwareDevelopersManual

18 7 intel486 dx processor

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Unformatted text preview: . . . . . . . . . . 6-6 INDEX-6 INDEX use in address translation. . . . . . . . . . . . . . .3-7 GDTR register description of . . . . . . . . . . . . . . 2-3, 2-10, 3-17 introduction to . . . . . . . . . . . . . . . . . . . . . . . .2-5 limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5 loading during initialization . . . . . . . . . . . . .8-12 storing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-18 GE (global exact breakpoint enable) flag, DR7 register. . . . . . . . . . . . . 15-5, 15-10 General-detect exception condition . . . . . . . .15-10 General-protection exception (#GP) 3-14, 4-7, 4-8, 4-14, 4-15, 5-17, 5-41, 6-7, 15-2, 18-14, 18-26, 18-27, 18-35, 18-37 General-purpose registers saved in TSS . . . . . . . . . . . . . . . . . . . . . . . .6-4 Global descriptor table register (see GDTR) Global descriptor table (see GDT) H HALT state . . . . . . . . . . . . . . . . . . . . . . . . . . .12-13 relationship to SMI interrupt . . . . . . . . . . . .12-3 Hardware reset description of . . . . . . . . . . . . . . . . . . . . . . . .8-1 processor state after reset . . . . . . . . . . . . . .8-2 state of MTRRs following . . . . . . . . . . . . . .9-18 value of SMBASE following . . . . . . . . . . . .12-4 Hexadecimal numbers . . . . . . . . . . . . . . . . . . . .1-7 HITM# line . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-5 HLT instruction . . . 2-22, 4-25, 5-33, 12-13, 12-14, 15-15 I ID (identification) flag, EFLAGS register 2-10, 18-6 IDIV instruction. . . . . . . . . . . . . . . . . . . 5-22, 18-26 IDT calling interrupt- and exception-handlers from . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-15 changing base and limit in real-address mode . . . . . . . . . . . . . . . . . . . . . . . . . . .16-6 description of . . . . . . . . . . . . . . . . . . . . . . .5-11 handling NMI interrrupts during initialization . . . . . . . . . . . . . . . . . . . . . .8-11 initializing, for protected-mode operation . .8-12 initializing, for real-address mode operation . . . . . . . . . . . . . . . . . . . . . . . .8-10 introduction to . . . . . . . . . . . . . . . . . . . . . . . .2-4 limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-28 structure in real-address mode . . . . . . . . . .16-7 task switching . . . . . . . . . . . . . . . . . . . . . . .6-10 task-gate descriptor . . . . . . . . . . . . . . . . . . .6-8 types of descriptors allowed . . . . . . . . . . . .5-13 use in real-address mode . . . . . . . . . . . . . .16-6 IDTR register description of . . . . . . . . . . . . . . . . . . 2-11, 5-13 introduction to . . . . . . . . . . . . . . . . . . . . . . . .2-4 limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5 loading in real-address mode . . . . . . . . . . .16-6 storing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-18 IE (invalid operation exception) flag, FPU status word . . . . . . . . . . . . . . . . . . . 18-9 IEEE 754 and 854 standards for floating-point arithmetic . . . . . . . . . . . . . . .18-9, 18-10 IF (interrupt enable) flag, EFLAGS register . . . 2-8, 5-8, 5-15, 5-18, 12-10, 16-6, 16-26 IN instruction. . . . . . . . . . . . . . . . . . . . .7-10, 18-36 INC instruction . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 Index field, segment selector . . . . . . . . . . . . . . 3-7 Inexact Result (Precision) Exception . . . . . . 11-21 Inexact result (precision) exception (#P) . . . 11-21 Inexact result, FPU . . . . . . . . . . . . . . . . . . . . . 11-4 INIT interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 Initial-count register, local APIC . . . . . . . . . . . 7-44 Initialization built-in self-test (BIST). . . . . . . . . . . . . .8-1, 8-2 CS register state following . . . . . . . . . . . . . 8-6 dual-processor (DP) bootup sequence for Pentium processors . . . . . . . . . . . . . . . . C-1 EIP register state following . . . . . . . . . . . . . 8-6 example. . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 first instruction executed . . . . . . . . . . . . . . . 8-6 FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 hardware reset . . . . . . . . . . . . . . . . . . . . . . 8-1 IDT, protected mode . . . . . . . . . . . . . . . . . 8-12 IDT, real-address mode . . . . . . . . . . . . . . 8-10 Intel486 SX processor and Intel 487 SX math coprocessor . . . . . . . . . . . . . . . . . . . 18-20 local APIC . . . . . . . . . . . . . . . . . . . . . . . . . 7-35 location of software-initialization code. . . . . 8-6 model and stepping information . . . . . . . . . 8-5 multiple-processor (MP) bootup sequence for P6 family processors . . . . . . . . . . . . . . . D-1 multitasking environment . . . . . . . . . . . . . 8-13 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 processor state after reset . . . . . . . . . . . . . 8-2 protected mode . . . . . . . . . . . . . . . . . . . . . 8-...
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