IntelSoftwareDevelopersManual

18 7 configuring the fpu environment

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Unformatted text preview: lization . . . . . . . . . . . . . .8-6 EM (emulation) flag, CR0 control register . . . 2-15, 5-30, 8-6, 8-8 EOI (end-of-interrupt register), local APIC . . . .7-33 Error code exception, description of . . . . . . . . . . . . . . .5-20 pushing on stack. . . . . . . . . . . . . . . . . . . .18-33 Error signals . . . . . . . . . . . . . . . . . . . . 18-12, 18-13 ERROR# input . . . . . . . . . . . . . . . . . . . . . . . .18-19 ERROR# output . . . . . . . . . . . . . . . . . . . . . . .18-19 ES0 and ES1 (event select) fields, CESR MSR (Pentium processor). . . . . . .15-20, A-12 ESP register, saving on call to exception or interrupt handler . . . . . . . . . . . . . . . . . . . . . . .5-15 ESR (error status register), local APIC . . . . . .7-42 ET (extension type) flag, CR0 control register .2-14 ET (extension type) flag, CR0 register . . . . . . .18-8 Event select field, PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family processors) . . . . 15-16 Exception handler calling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 defined . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 flag usage by handler procedure. . . . . . . . 5-18 machine-check exceptions (#MC). . . . . . 13-14 procedures . . . . . . . . . . . . . . . . . . . . . . . . 5-15 protection of handler procedures . . . . . . . 5-17 task . . . . . . . . . . . . . . . . . . . . . . . . . . .5-18, 6-3 Exception priority, FPU exceptions. . .11-13, 18-12 Exceptions alignment check . . . . . . . . . . . . . . . . . . . 18-13 classifications . . . . . . . . . . . . . . . . . . . . . . . 5-4 conditions checked during a task switch . . 6-13 coprocessor segment overrun. . . . . . . . . 18-14 description of. . . . . . . . . . . . . . . . . . . . .2-4, 5-1 device not available. . . . . . . . . . . . . . . . . 18-14 double fault . . . . . . . . . . . . . . . . . . . . . . . . 5-32 error code . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 floating-point error . . . . . . . . . . . . . . . . . . 18-14 general protection . . . . . . . . . . . . . . . . . . 18-14 handler mechanism. . . . . . . . . . . . . . . . . . 5-15 handler procedures . . . . . . . . . . . . . . . . . . 5-15 handling. . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 handling in real-address mode . . . . . . . . . 16-6 handling in SMM . . . . . . . . . . . . . . . . . . . 12-10 handling in virtual-8086 mode . . . . . . . . . 16-15 handling through a task gate in virtual-8086 mode . . . . . . . . . . . . . . . . . . . . . . . . . 16-20 handling through a trap or interrupt gate in virtual-8086 mode . . . . . . . . . . . . . . . 16-17 IDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 initializing for protected-mode operation . . 8-12 invalid opcode . . . . . . . . . . . . . . . . . . . . . . 18-6 masking debug exceptions . . . . . . . . . . . . . 5-9 masking when switching stack segments . 5-10 notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 overview of . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 priorities among simultaneous exceptions and interrupts . . . . . . . . . . . . . . . . . . . . . . . 5-10 priority of . . . . . . . . . . . . . . . . . . . . . . . . . 18-27 reference information on all exceptions . . 5-21 restarting a task or program . . . . . . . . . . . . 5-7 segment not present . . . . . . . . . . . . . . . . 18-14 sources of . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 summary of . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Executable code segment, size . . . . . . . . . . . 3-12 Expand-down data segment type . . . . . . . . . . 3-12 External bus errors, detected with machine-check architecture. . . . . . . . . . . . . . . . . . 13-11 F F2XM1 instruction. . . . . . . . . . . . . . . . . . . . . 18-16 Fast string operations . . . . . . . . . . . . . . . . . . . . 7-9 INDEX-5 INDEX Faults description of . . . . . . . . . . . . . . . . . . . . . . . .5-4 restarting a program or task after . . . . . . . . .5-7 FCMOVcc instructions . . . . . . . . . . . . . . . . . . .18-3 FCOMI instruction . . . . . . . . . . . . . . . . . . . . . .18-3 FCOMIP instruction . . . . . . . . . . . . . . . . . . . . .18-3 FCOS instruction . . . . . . . . . . . . . . . . . . . . . .18-16 FDISI instruction (obsolete) . . . . . . . . . . . . . .18-18 FDIV instruction . . . . . . . . . . . . . . . . . 18-13, 18-15 FE (fixed MTRRs enabled) flag, MTRRdefType register . . . . . . . . . . . . . . . . . . . . . . .9-22 Feature determination, of processor . . . . . . . .18-2 Feature information, processor . . . . . . . . . . . .18-2 FENI instruction (obsolete). . . . . . . . . . . . . . .18-18 FINIT/FNINIT instructions . . . . . . . . . . 18-8, 18-19 FIX (fixed range registers supported) flag, MTRRcap register . . . . . . . . . . . . . .9-21 Fixed-range MTRRs description of . . . . . . . . . . . . . . . . . . . . . . .9-22 mapping to physical memory . . . . . . . . . ....
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

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