IntelSoftwareDevelopersManual

18 9 cache control

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Unformatted text preview: . .17-1 8086 emulation, support for . . . . . . . . . . . . . . . . .16-1 processor, exceptions and interrupts . . . . .16-8 8086/8088 processor . . . . . . . . . . . . . . . . . . . .18-7 8087 math coprocessor . . . . . . . . . . . . . . . . . .18-7 82489DX, software visible differences between the local APIC on a Pentium Pro processor and the 82489DX . . . . . . . . . . . . . . .7-44 bus message format . . . . . . . . . . . . . . . . . 7-37 description of. . . . . . . . . . . . . . . . . . . . . . . 7-13 diagram of . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 EOI message format . . . . . . . . . . . . . . . . . 7-37 nonfocused lowest priority message . . . . . 7-38 short message format . . . . . . . . . . . . . . . . 7-37 SMI message . . . . . . . . . . . . . . . . . . . . . . 12-2 status cycles . . . . . . . . . . . . . . . . . . . . . . . 7-40 structure of . . . . . . . . . . . . . . . . . . . . . . . . 7-14 APIC (see also I/O APIC or Loal APIC) APIC_BASE_MSR . . . . . . . . . . . . . . . . . . . . . 7-19 APR (arbitration priority register), local APIC . 7-32 Arbitration APIC bus . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36 priority, local APIC. . . . . . . . . . . . . . . . . . . 7-22 ARPL instruction. . . . . . . . . . . . . . . . . . .2-20, 4-30 Atomic operations automatic bus locking . . . . . . . . . . . . . . . . . 7-3 effects of a locked operation on internal processor caches. . . . . . . . . . . . . . . . . . 7-6 guaranteed, description of. . . . . . . . . . . . . . 7-2 overview of . . . . . . . . . . . . . . . . . . . . . .7-2, 7-3 software-controlled bus locking. . . . . . . . . . 7-4 Auto HALT restart field, SMM . . . . . . . . . . . . . . . . . . . . . . . . 12-13 SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13 Automatic bus locking. . . . . . . . . . . . . . . . . . . . 7-3 A A (accessed) flag, page-table entry . . . . . . . . .3-27 A20M# signal . . . . . . . . . . . . . . . . . . . . 16-3, 18-35 Aborts description of . . . . . . . . . . . . . . . . . . . . . . . .5-5 restarting a program or task after . . . . . . . . .5-7 AC (alignment check) flag, EFLAGS register . . . . . . 2-9, 5-50, 18-6 Access rights checking . . . . . . . . . . . . . . . . . . . . . . . . . . .2-20 checking caller privileges . . . . . . . . . . . . . .4-28 description of . . . . . . . . . . . . . . . . . . . . . . .4-26 invalid values . . . . . . . . . . . . . . . . . . . . . .18-24 ADC instruction . . . . . . . . . . . . . . . . . . . . . . . . .7-4 ADD instruction . . . . . . . . . . . . . . . . . . . . . . . . .7-4 Address size prefix . . . . . . . . . . . . . . . . . . . . . . . . . .17-2 space, of task . . . . . . . . . . . . . . . . . . . . . . .6-17 Address translation 2-MByte pages . . . . . . . . . . . . . . . . . . . . . .3-32 4-KByte pages . . . . . . . . . . . . . . . . . 3-20, 3-30 4-MByte pages . . . . . . . . . . . . . . . . . . . . . .3-21 in real-address mode . . . . . . . . . . . . . . . . .16-3 logical to linear . . . . . . . . . . . . . . . . . . . . . . .3-7 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-6 Addressing, segments . . . . . . . . . . . . . . . . . . . .1-7 Advanced programmable interrupt controller (see APIC, I/O APIC, or Loal APIC) Alignment alignment check exception . . . . . . . . . . . . .5-50 checking . . . . . . . . . . . . . . . . . . . . . . . . . . .4-30 exception . . . . . . . . . . . . . . . . . . . . . . . . .18-13 Alignment check exception (#AC) . . . 5-50, 18-13, 18-26 AM (alignment mask) flag, CR0 control register . . . . . . . 2-14, 18-22 AND instruction . . . . . . . . . . . . . . . . . . . . . . . . .7-4 APIC Base field, APIC_BASE_MSR . . . . . . . .7-19 APIC bus arbitration mechanism and protocol . . . . . .7-36 bus arbitration . . . . . . . . . . . . . . . . . . . . . . .7-15 B B (busy) flag, TSS descriptor . 6-7, 6-12, 6-16, 7-3 B (default stack size) flag, segment descriptor . . . 17-2, 18-34 B0-B3 (breakpoint condition detected) flags, DR6 register . . . . . . . . . . . . . . . . . . 15-4 Backlink (see Previous task link) Base address fields, segment descriptor . . . . 3-11 BD (debug register access detected) flag, DR6 register . . . . . . . . . . . . .15-4, 15-10 Binary numbers . . . . . . . . . . . . . . . . . . . . . . . . 1-7 BINIT# signal . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 Bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 BOUND instruction . . . . . . . . . . . . . . . . . .5-3, 5-27 BOUND range exceeded exception (#BR) . . . 5-27 BP0#, BP1#, BP2#, and BP3# pins . . . . . . . 15-12 Breakpoint exception (#BP) 5-3, 5-25, 15-1, 15-11 Breakpoints breakpoint exception (#BP). . . . . . . . . . . . 15-1 data breakpoint . . . . . . . . . . . . . . . . . . . . . 15-7 data breakpoint exception conditions . . . . 15-9 description of. . . . . . . . . . . . . . . . . . . . . . . 15-1 DR0-DR3 debug registers. . . . . . . . . . . . . 15-4 example. . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 INDEX-1 INDEX...
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