IntelSoftwareDevelopersManual

2 5 segment descriptor layout of

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Unformatted text preview: model . . . . . . . . . . . . . . . . . . . . . . 3-3 code type. . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 combining segment and page-level protection . . . . . . . . . . . . . . . . . . . . . . . 4-33 combining with paging. . . . . . . . . . . . . . . . . 3-6 data type . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 defined . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 disabling protection of . . . . . . . . . . . . . . . . . 4-2 enabling protection of . . . . . . . . . . . . . . . . . 4-2 mapping to pages . . . . . . . . . . . . . . . . . . . 3-39 multisegment usage model . . . . . . . . . . . . . 3-5 protected flat model. . . . . . . . . . . . . . . . . . . 3-4 segment-level protection . . . . . . . . . . . . . . . 4-2 segment-not-present exception. . . . . . . . . 5-37 system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 types, checking access rights . . . . . . . . . . 4-26 typing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 using . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 wraparound . . . . . . . . . . . . . . . . . . . . . . . 18-35 Self-interrupts, local APIC . . . . . . . . . . . . . . . 7-25 Self-modifying code, effect on caches . . . . . . 9-15 Serializing instructions . . . . . . . . . . . . .7-11 , 18-19 SF (stack fault) flag, FPU status word . . . . . . 18-9 SGDT instruction . . . . . . . . . . . . . . . . . .2-20, 3-18 Shutdown resulting from double fault. . . . . . . . . . . . . 5-33 resulting from out of IDT limit condition. . . 5-33 SIDT instruction . . . . . . . . . . . . . . 2-20, 3-18, 5-13 Single-stepping breakpoint exception condition . . . . . . . . 15-10 on branches . . . . . . . . . . . . . . . . . . . . . . 15-14 on exceptions . . . . . . . . . . . . . . . . . . . . . 15-14 on interrupts . . . . . . . . . . . . . . . . . . . . . . 15-14 TF (trap) flag, EFLAGS register . . . . . . . 15-10 SLDT instruction . . . . . . . . . . . . . . . . . . . . . . . 2-20 SLTR instruction . . . . . . . . . . . . . . . . . . . . . . . 3-18 SMBASE default value . . . . . . . . . . . . . . . . . . . . . . . 12-4 relocation of. . . . . . . . . . . . . . . . . . . . . . . 12-14 SMI handler description of. . . . . . . . . . . . . . . . . . . . . . . 12-1 execution environment for. . . . . . . . . . . . . 12-8 exiting from . . . . . . . . . . . . . . . . . . . . . . . . 12-3 location in SMRAM . . . . . . . . . . . . . . . . . . 12-4 SMI interrupt . . . . . . . . . . . . . . . . . . . . . .2-22, 7-13 description of. . . . . . . . . . . . . . . . . . .12-1, 12-2 priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 switching to SMM . . . . . . . . . . . . . . . . . . . 12-2 SMI# pin . . . . . . . . . . . . . . . . . . . . 5-2, 12-2, 12-15 SMM auto halt restart . . . . . . . . . . . . . . . . . . . . 12-13 executing the HLT instruction in . . . . . . . 12-14 exiting from . . . . . . . . . . . . . . . . . . . . . . . . 12-3 handling exceptions and interrupts . . . . . 12-10 I/O instruction restart. . . . . . . . . . . . . . . . 12-15 native 16-bit mode. . . . . . . . . . . . . . . . . . . 17-1 overview of . . . . . . . . . . . . . . . . . . . . . . . . 12-1 revision identifier . . . . . . . . . . . . . . . . . . . 12-12 INDEX-15 INDEX revision identifier field . . . . . . . . . . . . . . . .12-12 switching to . . . . . . . . . . . . . . . . . . . . . . . . .12-2 switching to from other operating modes . .12-2 using FPU in . . . . . . . . . . . . . . . . . . . . . . .12-11 SMRAM caching . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-7 description of . . . . . . . . . . . . . . . . . . . . . . .12-1 state save map . . . . . . . . . . . . . . . . . . . . . .12-5 structure of . . . . . . . . . . . . . . . . . . . . . . . . .12-4 SMSW instruction. . . . . . . . . . . . . . . . . . . . . . .2-20 SNaN compatibility, Intel Architecture processors. . . . . . . . . . . . . . . . 18-10, 18-17 Snooping mechanism. . . . . . . . . . . . . . . . . 7-8, 9-5 Software interrupts . . . . . . . . . . . . . . . . . . . . . . .5-3 Software-controlled bus locking . . . . . . . . . . . . .7-4 Split pages . . . . . . . . . . . . . . . . . . . . . . . . . . .18-18 Spurious interrupt, local APIC . . . . . . . . . . . . .7-33 SS register, saving on call to exception or interrupt handler . . . . . . . . . . . . . . . . . . . . . . .5-15 Stack fault exception (#SS) . . . . . . . . . . . . . . .5-39 Stack fault, FPU . . . . . . . . . . . . . . . . . . 18-9, 18-16 Stack overflow exception, FPU . . . . . . . . . . .11-17 Stack pointers privilege level 0, 1, and 2 stacks. . . . . . . . . .6-6 size of . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12 Stack segments privilege level checks when loading the SS register . . . . . . . . . . . . . . . . . . . . . . . . .4-12 size of stack pointer . . . . . . . . . . . . . . . . . .3-12 Stack switching inter-privilege level calls . . . . . . . . . . . . . . .4-21 masking ex...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.

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