IntelSoftwareDevelopersManual

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Unformatted text preview: . . . . . 2-17, 3-27, 18-21, 18-23 PhysBase field, MTRRphysBasen register. . . 9-24 Physical address extension access full extended physical address space . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 description of. . . . . . . . . . . . . . . . . . . . . . . 3-29 page-directory entries . . . . . . . . . . . . . . . . 3-33 page-table entries . . . . . . . . . . . . . . . . . . . 3-33 Physical address space defined . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 description of. . . . . . . . . . . . . . . . . . . . . . . . 3-6 mapped to a task. . . . . . . . . . . . . . . . . . . . 6-17 Physical addressing . . . . . . . . . . . . . . . . . . . . . 2-5 Physical destination mode, local APIC . . . . . . 7-20 Physical memory mapping of with fixed-range MTRRs . . . . . 9-23 mapping of with variable-range MTRRs . . 9-23 PhysMask, MTRRphysMaskn register . . . . . . 9-24 PM0/BP0 and PM1/BP1 (performance-monitor) pins (Pentium processor) . 15-20, 15-21, 15-22 Pointers code-segment pointer size . . . . . . . . . . . . 17-5 limit checking. . . . . . . . . . . . . . . . . . . . . . . 4-28 validation . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25 POP instruction. . . . . . . . . . . . . . . . . . . . . . . . . 3-9 POPF instruction . . . . . . . . . . . . . . . . . .5-9, 15-10 PPR (processor priority register), local APIC . 7-32 INDEX-13 INDEX Previous task link field, TSS. . . . . . 6-4, 6-14, 6-16 Priority levels, APIC interrupts . . . . . . . . . . . . .7-15 Privilege levels checking when accessing data segments . .4-9 checking, for call gates . . . . . . . . . . . . . . . .4-17 checking, when transferring program control between code segments . . . . . . . . . . . .4-12 description of . . . . . . . . . . . . . . . . . . . . . . . .4-8 protection rings . . . . . . . . . . . . . . . . . . . . . . .4-9 Privileged instructions . . . . . . . . . . . . . . . . . . .4-25 Processor identification earlier Intel architecture processors . . . . . .9-33 Processor management initialization . . . . . . . . . . . . . . . . . . . . . . . . . .8-1 local APIC . . . . . . . . . . . . . . . . . . . . . . . . . .7-13 overview of . . . . . . . . . . . . . . . . . . . . . . . . . .7-1 snooping mechanism . . . . . . . . . . . . . . . . . .7-8 processor number . . . . . . . . . . . . . . . . . . B-4, B-9 Processor ordering, description of . . . . . . . . . . .7-7 Protected mode IDT initialization . . . . . . . . . . . . . . . . . . . . .8-12 initialization for . . . . . . . . . . . . . . . . . . . . . .8-11 mixing 16-bit and 32-bit code modules . . . .17-2 mode switching . . . . . . . . . . . . . . . . . . . . . .8-13 PE flag, CR0 register . . . . . . . . . . . . . . . . . .4-2 switching to . . . . . . . . . . . . . . . . . . . . . 4-2, 8-14 system data structures required during initialization . . . . . . . . . . . . . . . . . 8-11, 8-12 Protection combining segment and page-level protection. . . . . . . . . . . . . . . . . . . . . . . .4-33 disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2 enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2 flags used for page-level protection . . . . . . .4-2 flags used for segment-level protection . . . .4-2 of exception- and interrupt-handler procedures 5-17 overview of . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 page level . . . . . . . . . . . . . . . . . . . . . . 4-2, 4-32 page level, overriding . . . . . . . . . . . . . . . . .4-32 page level, overview . . . . . . . . . . . . . . . . . .4-30 page-level protection flags . . . . . . . . . . . . .4-31 read/write, page level . . . . . . . . . . . . . . . . .4-32 segment level . . . . . . . . . . . . . . . . . . . . . . . .4-2 user/supervisor type . . . . . . . . . . . . . . . . . .4-31 Protection rings . . . . . . . . . . . . . . . . . . . . . . . . .4-9 PS (page size) flag, page-table entry. . . . . . . .3-27 PSE (page size extension) flag, CR4 control register . . . 2-17, 3-19, 3-21, 3-22, 9-17, 18-22, 18-23 Pseudo-infinity . . . . . . . . . . . . . . . . . . . . . . . .18-10 Pseudo-NaN. . . . . . . . . . . . . . . . . . . . . . . . . .18-10 Pseudo-zero. . . . . . . . . . . . . . . . . . . . . . . . . .18-10 PUSH instruction . . . . . . . . . . . . . . . . . . . . . . .18-7 PUSHF instruction . . . . . . . . . . . . . . . . . . 5-9, 18-7 PVI (protected-mode virtual interrupts) flag, CR4 control register . . . . . . . . . . . 2-17 , 18-22 PWT (page-level write-through) flag CR3 control register . 2-16, 9-12, 18-22, 18-31 page-directory entries . . . . . . . . 8-8, 9-12, 9-32 page-table entries . . . . . 8-8, 9-12, 9-32, 18-32 page-table entry . . . . . . . . . . . . . . . . . . . . 3-26 Q QNaN compatibility, Intel Architecture processors . . . . . . . . . . . . . . . . . . . . . 18-10 R RC (rounding control) field, FPU control word . . . . . . . . . . . . . . . . . . . .11-3, 11-4 RDMSR instruction2-23, 4-25, 9-20, 15-13, 15-15, 15-16, 15-18, 15-20, 18-4, 18-38 RDPMC instruction2-22, 4-25, 15-...
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