IntelSoftwareDevelopersManual

4 8 protection rings

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Unformatted text preview: . . . . . . . . . . . . . . . . . . . . 2-5 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 PG flag, CR0 control register . . . . . . . . . . . 4-2 Pages, split . . . . . . . . . . . . . . . . . . . . . . . . . . 18-18 Page-table base address field, page-directory entry . . . . . . . . . . . . . . . . . . . . . . . . 3-25 O Obsolete instructions . . . . . . . . . . . . . . 18-5, 18-18 OE (numeric overflow exception) flag, FPU status word . . . . . . . . . . . . . . . . . . 11-18, 11-19 OF flag, EFLAGS register . . . . . . . . . . . . . . . .5-26 Opcodes undefined . . . . . . . . . . . . . . . . . . . . . . . . . .18-6 Operand instruction . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7 INDEX-12 INDEX Page-table entries automatic bus locking while updating . . . . . .7-4 caching in TLBs . . . . . . . . . . . . . . . . . . . . . .9-4 effect of implicit caching on. . . . . . . . . . . . .9-16 page base address field . . . . . . . . . . . . . . .3-25 R/W (read/write) flag. . . . . . . . . . 4-2, 4-3, 4-32 structure of . . . . . . . . . . . . . . . . . . . . . . . . .3-23 U/S (user/supervisor) flag . . . . . . 4-2, 4-3, 4-31 Paging combining segment and page-level protection. . . . . . . . . . . . . . . . . . . . . . . .4-33 combining with segmentation . . . . . . . . . . . .3-6 defined . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1 initializing . . . . . . . . . . . . . . . . . . . . . . . . . .8-12 introduction to . . . . . . . . . . . . . . . . . . . . . . . .2-5 large page size MTRR considerations . . . .9-32 linear address translation (4-KByte pages).3-20 linear address translation (4-MByte pages) 3-21 mapping segments to pages. . . . . . . . . . . .3-39 mixing 4-KByte and 4-MByte pages . . . . . .3-22 page boundaries regarding TSS. . . . . . . . . .6-6 page-fault exception . . . . . . . . . . . . . . . . . .5-44 page-level protection . . . . . . . . . . . . . 4-2, 4-30 page-level protection flags . . . . . . . . . . . . .4-31 virtual-8086 tasks . . . . . . . . . . . . . . . . . . .16-10 Parameter passing, between 16- and 32-bit call gates 17-7 translation, between 16- and 32-bit code segments. . . . . . . . . . . . . . . . . . . . . . . .17-8 PBi (performance monitoring/breakpoint pins) flags, DebugCtlMSR register . . . . . . . . . .15-12 PC (pin control) flag, PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family processors) . . . .15-17 PC0 and PC1 (pin control) fields, CESR MSR (Pentium processor). . . . . . . . . . . .15-21 PCD (page-level cache disable) flag CR3 control register . 2-16, 9-12, 18-22, 18-31 page-directory entries . . . 8-8, 9-12, 9-13, 9-32 page-table entries . 3-26, 8-8, 9-12, 9-13, 9-32, 18-32 PCE (performance-monitoring counter enable) flag, CR4 control register . . 2-18, 4-25, 18-21 PCE (performance-monitoring counter enable) flag, CR4 control register (P6 family processors) . . . . . . . . . . . . . . . . . .15-18 PDBR (see CR3 control register) PE (inexact result exception) flag, FPU status word . . . . . . . . . . . . . . . . . . . 11-4, 11-21 PE (protection enable) flag, CR0 control register . . . . . 2-16, 4-2, 8-13, 8-14, 12-8 Pentium Pro processor. . . . . . . . . . . . . . . . . . . .1-1 Pentium processors . . . . . . . . . . . . . . . . . . . . .18-7 list of events counted with performance-monitoring counters . . . . A-12 performance-monitoring counters. . . . . . .15-20 PerfCtr0 and PerfCtr1 MSRs (P6 family processors) . . . . . . . . . . . . . . . . . .15-16 PerfCtr0 MSR and PerfCtr1 MSRs (P6 family processors). . . . . . . . . . . . . . . . . . 15-18 PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family processors). . . . . . . . . . . . . . . . . . 15-16 Performance-monitoring counters description of. . . . . . . . . . . . . . . . . . . . . . 15-15 events that can be counted (P6 family processors) . . . . . . . . . . . . . . . . . . . . . . A-1 events that can be counted (Pentium processors) . . . . . . . . . . . . . . . 15-22, A-12 introduction of in Intel Architecture processors . . . . . . . . . . . . . . . . . . . . . 18-40 monitoring counter overflow (P6 family processors) . . . . . . . . . . . . . . . . . . . . 15-19 overflow, monitoring (P6 family processors) . . . . . . . . . . . . . . . . . . . . 15-19 overview of . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 P6 family processors. . . . . . . . . . . . . . . . 15-15 Pentium II processor . . . . . . . . . . . . . . . . 15-15 Pentium Pro processor . . . . . . . . . . . . . . 15-15 Pentium processor . . . . . . . . . . . . . . . . . 15-20 reading . . . . . . . . . . . . . . . . . . . . . .2-22, 15-18 setting up (P6 family processors) . . . . . . 15-16 software drivers for . . . . . . . . . . . . . . . . . 15-18 starting and stopping. . . . . . . . . . . . . . . . 15-18 Performance-monitoring events list of events . . . . . . . . . . . . . . . . . . . . . . . . A-1 PG (paging) flag, CR0 control register . 2-13, 3-19, 3-26, 4-2, 8-13, 8-14, 12-8, 18-32 PGE (page global enable) flag, CR4 control register ....
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