IntelSoftwareDevelopersManual

4

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-34 Microcode Update Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-43 Parameters for the Presence Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-44 Parameters for the Write Update Data Function. . . . . . . . . . . . . . . . . . . . . . .8-45 Parameters for the Control Update Sub-function . . . . . . . . . . . . . . . . . . . . . .8-48 Mnemonic Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-48 Parameters for the Read Microcode Update Data Function. . . . . . . . . . . . . .8-49 Return Code Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-50 Characteristics of the Caches, TLBs, and Write Buffer in Intel Architecture Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3 Methods of Caching Available in P6 Family, Pentium ®, and Intel486™ Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-6 MESI Cache Line States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-9 Cache Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-11 TABLE OF TABLES Table 9-5. Table 9-6. Table 9-7. Table 9-8. Table 9-9. Table 9-10. Table 10-1. Table 10-2. Table 11-1. Table 11-2. Table 11-3. Table 11-4. Table 11-5. Table 11-6. Table 11-7. Table 11-8. Table 11-9. Table 12-1. Table 12-2. Table 12-3. Table 12-4. Table 13-1. Table 13-2. Table 13-3. Table 13-4. Table 13-5. Table 13-6. Table 13-7. Table 14-1. Table 14-2. Table 15-1. Table 15-2. Table 16-1. Table 16-2. Table 17-1. Table 18-1. Table 18-1. Table 18-2. Table A-1. Table A-2. Table B-1. Effective Memory Type Depending on MTRR, PCD, and PWT Settings . . . .9-14 MTRR Memory Types and Their Properties . . . . . . . . . . . . . . . . . . . . . . . . . .9-19 Address Mapping for Fixed-Range MTRRs . . . . . . . . . . . . . . . . . . . . . . . . . .9-23 PAT Indexing and Values After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-35 Effective Memory Type Depending on MTRRs and PAT . . . . . . . . . . . . . . . .9-37 PAT Memory Types and Their Properties . . . . . . . . . . . . . . . . . . . . . . . . . . .9-38 Effects of MMX™ Instructions on FPU State . . . . . . . . . . . . . . . . . . . . . . . . .10-3 Effect of the MMX™ and Floating-Point Instructions on the FPU Tag Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3 SIMD Floating-point Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-2 Rounding Control Field (RC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-4 Rounding of Positive Numbers Greater than the Maximum Positive Finite Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-5 Rounding of Negative Numbers Smaller than the Maximum Negative Finite Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-5 CPUID Bits for Streaming SIMD Extensions Support . . . . . . . . . . . . . . . . . .11-6 CR4 Bits for Streaming SIMD Extensions Support . . . . . . . . . . . . . . . . . . . .11-6 Streaming SIMD Extensions Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-12 Invalid Arithmetic Operations and the Masked Responses to Them . . . . . .11-18 Masked Responses to Numeric Overflow . . . . . . . . . . . . . . . . . . . . . . . . . .11-20 SMRAM State Save Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-5 Processor Register Initialization in SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-9 Auto HALT Restart Flag Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-14 I/O Instruction Restart Field Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-16 Simple Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-9 General Forms of Compound Error Codes. . . . . . . . . . . . . . . . . . . . . . . . . . .13-9 Encoding for TT (Transaction Type) Sub-Field. . . . . . . . . . . . . . . . . . . . . . .13-10 Level Encoding for LL (Memory Hierarchy Level) Sub-Field . . . . . . . . . . . .13-10 Encoding of Request (RRRR) Sub-Field . . . . . . . . . . . . . . . . . . . . . . . . . . .13-10 Encodings of PP, T, and II Sub-Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-11 Encoding of the MCi_STATUS Register for External Bus Errors . . . . . . . .13-11 Small and Large General-Purpose Register Pairs . . . . . . . . . . . . . . . . . . . . .14-7 Pairable Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-14 Breakpointing Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-7 Debug Exception Conditions . . . . . . . . . . . . ....
View Full Document

This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.

Ask a homework question - tutors are online