IntelSoftwareDevelopersManual

5 11 handling nmi

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Unformatted text preview: .9-23 Flat model, local APIC . . . . . . . . . . . . . . . . . . .7-21 Flat segmentation model . . . . . . . . . . . . . . 3-3, 3-4 FLD instruction . . . . . . . . . . . . . . . . . . . . . . . .18-16 FLDENV instruction . . . . . . . . . . . . . . . . . . . .18-14 FLDL2E instruction. . . . . . . . . . . . . . . . . . . . .18-17 FLDL2T instruction. . . . . . . . . . . . . . . . . . . . .18-17 FLDLG2 instruction . . . . . . . . . . . . . . . . . . . .18-17 FLDLN2 instruction . . . . . . . . . . . . . . . . . . . .18-17 FLDPI instruction . . . . . . . . . . . . . . . . . . . . . .18-17 Floating-point error exception (#MF) . . 5-48, 5-53, 18-14 Floating-point exceptions denormal operand exception . . . . 11-19, 18-11 division-by-zero. . . . . . . . . . . . . . . . . . . . .11-18 exception conditions . . . . . . . . . . . . . . . . .11-16 exception priority. . . . . . . . . . . . . . . . . . . .11-13 inexact result (precision). . . . . . . . . . . . . .11-21 invalid arithmetic operand. . . . . . . . . . . . .11-17 invalid operation . . . . . . . . . . . . . . . . . . . .18-17 numeric overflow. . . . . . . . . . . . . . 11-19, 18-11 numeric underflow . . . . . . . . . . . . 11-20, 18-12 saved CS and EIP values . . . . . . . . . . . . .18-12 software handling . . . . . . . . . . . . . . . . . . .11-15 stack underflow. . . . . . . . . . . . . . . . . . . . .11-17 FLUSH# pin . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2 Focus processor, local APIC . . . . . . . . . . . . . .7-22 FPATAN instruction . . . . . . . . . . . . . . . . . . . .18-16 FPREM instruction . . . . . . . . . . 18-9, 18-13, 18-15 FPREM1 instruction . . . . . . . . . . . . . . . 18-9, 18-15 FPTAN instruction . . . . . . . . . . . . . . . . 18-9, 18-15 FPU compatibility with Intel Architecture FPUs and math coprocessors . . . . . . . . . . . . . . . .18-7 configuring the FPU environment . . . . . . . . .8-6 device-not-available exception . . . . . . . . . .5-30 error signals . . . . . . . . . . . . . . . . . 18-12, 18-13 floating-point error exception . . . . . . . . . . .5-48 initialization . . . . . . . . . . . . . . . . . . . . . . . . . .8-6 instruction synchronization . . . . . . . . . . . 18-19 setting up for software emulation of FPU functions . . . . . . . . . . . . . . . . . . . . . . . . 8-8 using in SMM . . . . . . . . . . . . . . . . . . . . . 12-11 FPU control word compatibility, Intel Architecture processors 18-9 RC field . . . . . . . . . . . . . . . . . . . . . . .11-3, 11-4 FPU status word condition code flags . . . . . . . . . . . . . . . . . 18-8 OE flag . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19 FPU tag word . . . . . . . . . . . . . . . . . . . . . . . . . 18-9 FRSTOR instruction . . . . . . . . . . . . . .18-13, 18-14 FSAVE/FNSAVE instructions . . . . . . .18-13, 18-18 FSCALE instruction . . . . . . . . . . . . . . . . . . . 18-15 FSIN instruction . . . . . . . . . . . . . . . . . . . . . . 18-16 FSINCOS instruction . . . . . . . . . . . . . . . . . . 18-16 FSQRT instruction . . . . . . . . . . . . . . .18-13, 18-15 FSTENV/FNSTENV instructions . . . . . . . . . 18-18 FTAN instruction. . . . . . . . . . . . . . . . . . . . . . . 18-9 FUCOM instruction . . . . . . . . . . . . . . . . . . . . 18-15 FUCOMI instruction . . . . . . . . . . . . . . . . . . . . 18-3 FUCOMIP instruction . . . . . . . . . . . . . . . . . . . 18-3 FUCOMP instruction. . . . . . . . . . . . . . . . . . . 18-15 FUCOMPP instruction . . . . . . . . . . . . . . . . . 18-15 FWAIT instruction . . . . . . . . . . . . . . . . . . . . . . 5-30 FXAM instruction . . . . . . . . . . . . . . . .18-16, 18-17 FXTRACT instruction . . . . . . . 18-11, 18-16, 18-17 G G (global) flag page-directory entries . . . . . . . . . . . .9-12, 9-17 page-table entries . . . . . . . . . . . . . . .9-12, 9-17 page-table entry . . . . . . . . . . . . . . . . . . . . 3-27 G (granularity) flag, segment descriptor 3-10, 3-12, 4-2, 4-5 G0-G3 (global breakpoint enable) flags, DR7 register . . . . . . . . . . . . . . . . . . 15-5 Gate descriptors call gates . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 description of. . . . . . . . . . . . . . . . . . . . . . . 4-16 Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 GD (general detect enable) flag, DR7 register . . . . . . . . . . . . .15-5, 15-10 GDT description of. . . . . . . . . . . . . . . . . . . .2-3, 3-17 index into with index field of segment selector . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 initializing. . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 pointers to exception and interrupt handlers . . . . . . . . . . . . . . . . . . . . . . . . 5-15 segment descriptors in . . . . . . . . . . . . . . . . 3-9 selecting with TI (table indicator) flag of segment selector . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 task switching . . . . . . . . . . . . . . . . . . . . . . 6-10 task-gate descriptor. . . . . . . . . . . . . . . . . . . 6-8 TSS descriptors. . . . . . . . . . . ....
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