IntelSoftwareDevelopersManual

6 6 page fault exception

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Unformatted text preview: . . . . . . . . . . . . . . . 8-13 linking tasks. . . . . . . . . . . . . . . . . . . . . . . . 6-14 mechanism, description of . . . . . . . . . . . . . 6-3 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 setting up TSS. . . . . . . . . . . . . . . . . . . . . . 8-13 INDEX-11 INDEX setting up TSS descriptor . . . . . . . . . . . . . .8-13 N NaN compatibility, Intel Architecture processors . . . 18-10 NE (numeric error) flag, CR0 control register. 2-14, 5-48, 8-6, 8-8, 18-22 NE (numeric error) flag, CR0 register . . . . . . .18-8 NEG instruction . . . . . . . . . . . . . . . . . . . . . . . . .7-4 NMI interrupt . . . . . . . . . . . . . . . . . . . . . 2-22, 7-13 description of . . . . . . . . . . . . . . . . . . . . . . . .5-2 handling during initialization . . . . . . . . . . . .8-10 handling in SMM . . . . . . . . . . . . . . . . . . . .12-10 handling multiple NMIs . . . . . . . . . . . . . . . . .5-8 masking . . . . . . . . . . . . . . . . . . . . . . . . . .18-28 receiving when processor is shutdown . . . .5-33 reference information . . . . . . . . . . . . . . . . .5-24 vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-4 NMI# pin. . . . . . . . . . . . . . . . . . . . . . . . . . 5-2, 5-24 Nonconforming code segments accessing . . . . . . . . . . . . . . . . . . . . . . . . . .4-14 C (conforming) flag . . . . . . . . . . . . . . . . . . .4-13 description of . . . . . . . . . . . . . . . . . . . . . . .3-14 Nonmaskable interrupt (see NMI) NOT instruction . . . . . . . . . . . . . . . . . . . . . . . . .7-4 Notation bit and byte order . . . . . . . . . . . . . . . . . . . . .1-6 exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . .1-8 hexadecimal and binary numbers. . . . . . . . .1-7 instruction operands . . . . . . . . . . . . . . . . . . .1-7 reserved bits . . . . . . . . . . . . . . . . . . . . . . . . .1-6 segmented addressing . . . . . . . . . . . . . . . . .1-7 Notational conventions. . . . . . . . . . . . . . . . . . . .1-5 NT (nested task) flag, EFLAGS register. 2-9, 6-10, 6-12, 6-14 Null segment selector, checking for . . . . . . . . . .4-7 Numeric overflow exception (#O). . . . 11-19, 18-11 Numeric underflow exception (#U). . . 11-20, 18-12 NV(invert)flag,PerfEvtSel0MSR(P6familyprocessors) 15-17 NW (not writethrough) flag, CR0 control register . . . . . . . . . 2-13, 8-8, 9-11, 9-12, 9-14, 9-31, 9-32 NW (not write-through) flag, CR0 control register . . . . . . . . . . 18-22, 18-23, 18-30 Operands operand-size prefix . . . . . . . . . . . . . . . . . . 17-2 OR instruction. . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 OS (operating system mode) flag, PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family processors). . . . . . . . . . . . . . . . . . 15-16 OUT instruction. . . . . . . . . . . . . . . . . . . . . . . . 7-10 OUTS instruction . . . . . . . . . . . . . . . . . . . . . 15-10 Overflow exception (#OF). . . . . . . . . . . . . . . . 5-26 Overflow, FPU stack. . . . . . . . . . . . . . . . . . . 11-17 P P (present) flag page-directory entry . . . . . . . . . . . . . . . . . 5-44 page-table entry . . . . . . . . . . . . . . . .3-25, 5-44 P (segment-present) flag, segment descriptor 3-12 P5_MC_ADDR MSR . . . . . . . . . . . . . .13-7, 13-16 P5_MC_TYPE MSR . . . . . . . . . . . . . . .13-7, 13-16 P6 family processors description of. . . . . . . . . . . . . . . . . . . . . . . . 1-1 list of events counted with performance-monitoring counters . . . . . A-1 PAE (physical address extension) flag, CR4 control register . 2-17, 3-19, 3-29, 18-21, 18-23 Page base address field, page-table entry . . . 3-25 Page directory base address. . . . . . . . . . . . . . . . . . . . . . . 3-23 base address (PDBR) . . . . . . . . . . . . . . . . . 6-6 description of. . . . . . . . . . . . . . . . . . . . . . . 3-20 introduction to . . . . . . . . . . . . . . . . . . . . . . . 2-5 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 setting up during initialization . . . . . . . . . . 8-13 Page frame (see Page) Page tables description of. . . . . . . . . . . . . . . . . . . . . . . 3-20 introduction to . . . . . . . . . . . . . . . . . . . . . . . 2-5 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 setting up during initialization . . . . . . . . . . 8-13 Page-directory entries automatic bus locking while updating . . . . . 7-4 caching in TLBs. . . . . . . . . . . . . . . . . . . . . . 9-4 page-table base address field . . . . . . . . . . 3-25 R/W (read/write) flag . . . . . . . . . . 4-2 , 4-3, 4-32 structure of . . . . . . . . . . . . . . . . . . . . . . . . 3-23 U/S (user/supervisor) flag . . . . . . 4-2, 4-3, 4-31 Page-directory-pointer (PDPTR) table . . . . . . 3-30 Page-fault exception (#PF). . . . . 3-18, 5-44, 18-26 Pages descripiton of. . . . . . . . . . . . . . . . . . . . . . . 3-20 disabling protection of . . . . . . . . . . . . . . . . . 4-2 enabling protection of . . . . . . . . . . . . . . . . . 4-2 introduction to . . ....
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