IntelSoftwareDevelopersManual

7 19 apr arbitration priority

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Unformatted text preview: . . . . . . . . . . . . . . . . . . 18-27 restarting a task or program . . . . . . . . . . . . 5-7 software. . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55 summary of . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 user defined . . . . . . . . . . . . . . . . . . . .5-4, 5-55 valid APIC interrupts . . . . . . . . . . . . . . . . . 7-15 vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 INTn instruction . . . . . . . . . . . . . . . . . . . . . . 15-10 INTO instruction . . . . . . . . . . 3-9, 5-3, 5-26, 15-10 INTR# pin . . . . . . . . . . . . . . . . . . . . . . . . . .5-2, 5-8 Invalid arithmetic operand exception (#IA), FPU description of. . . . . . . . . . . . . . . . . . . . . . 11-17 Invalid opcode exception (#UD) . 5-28, 12-3, 15-4, 18-6, 18-13 Invalid operation exception. . . . . . . . . . . . . . 11-17 Invalid operation exception, FPU . . . .18-13, 18-17 Invalid TSS exception (#TS). . . . . . . . . . .5-35, 6-7 Invalid-opcode exception (#UD) . . . . .18-25, 18-26 INVD instruction . . . . 2-21, 4-25, 7-12, 9-15, 18-5 INVLPG instruction . . . . . . . 2-21, 4-25, 7-12, 18-5 IOPL (I/O privilege level) field, EFLAGS register description of. . . . . . . . . . . . . . . . . . . . . . . . 2-8 restoring on return from exception or interrupt h andler. . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 sensitive instructions in virtual-8086 mode . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 IRET instruction . . 3-9, 5-8, 5-9, 5-15, 5-18, 6-10, 6-12, 7-12, 16-6, 16-27 IRETD instruction . . . . . . . . . . . . . . . . . . . . . . 7-12 IRR (interrupt request register), local APIC . . 7-30 ISR (in-service register), local APIC . . . . . . . . 7-30 I/O breakpoint exception conditions . . . . . . . . 15-9 in virtual-8086 mode . . . . . . . . . . . . . . . . 16-14 instruction restart flag, SMM revision indentifier field . . . . . . . . . . . . . . . . . . . . .12-15, 12-16 instructions, restarting following an SMI interrupt . . . . . . . . . . . . . . . . . . . . . . . 12-15 I/O permission bit map, TSS . . . . . . . . . . . . 6-6 map base address field, TSS . . . . . . . . . . . 6-6 I/O APIC bus arbitration . . . . . . . . . . . . . . . . . . . . . . 7-15 description of. . . . . . . . . . . . . . . . . . . . . . . 7-13 INDEX external interrupts . . . . . . . . . . . . . . . . . . . . .5-2 interrupt sources . . . . . . . . . . . . . . . . . . . . .7-15 relationship of local APIC to I/O APIC . . . .7-14 valid interrupts . . . . . . . . . . . . . . . . . . . . . .7-15 J JMP instruction. . 3-9, 4-12, 4-13, 4-17, 6-3, 6-10, 6-12 K KEN# pin . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-39 L L0-L3 (local breakpoint enable) flags, DR7 register. . . . . . . . . . . . . . . . . . .15-5 L1 (level 1) cache description of . . . . . . . . . . . . . . . . . . . . . . . .9-2 disabling . . . . . . . 9-4, 9-5, 9-8, 9-9, 9-15, 9-19 introduction of . . . . . . . . . . . . . . . . . . . . . .18-30 MESI cache protocol. . . . . . . . . . . . . . . . . . .9-9 L2 (level 2) cache description of . . . . . . . . . . . . . . . . . . . . . . . .9-2 disabling . . . . . . . 9-4, 9-5, 9-8, 9-9, 9-15, 9-19 introduction of . . . . . . . . . . . . . . . . . . . . . .18-30 MESI cache protocol. . . . . . . . . . . . . . . . . . .9-9 LAR instruction. . . . . . . . . . . . . . . . . . . . 2-20, 4-26 Larger page sizes introduction of . . . . . . . . . . . . . . . . . . . . . .18-32 support for. . . . . . . . . . . . . . . . . . . . . . . . .18-23 Last branch, interrupt, and exception recording description of . . . . . . . . . . . . . . . . . . . . . .15-11 initialization . . . . . . . . . . . . . . . . . . . . . . . .15-14 LastBranchFromIP MSR . . . . . 15-1, 15-13, 15-14 LastBranchToIP MSR . . . . . . . 15-1, 15-13, 15-14 LastExceptionFromIP MSR . . . 15-2, 15-13, 15-14 LastExceptionToIP MSR . . . . . 15-2, 15-13, 15-14 LBR (last branch/interrupt/exception) flag, DebugCtlMSR register . . . 15-11, 15-13, 15-14 LDR (logical destination register), local APIC .7-20 LDS instruction. . . . . . . . . . . . . . . . . . . . . 3-9, 4-10 LDT associated with a task. . . . . . . . . . . . . . . . . .6-3 description of . . . . . . . . . . . . . . . . . . . . . . .3-18 index into with index field of segment selector . . . . . . . . . . . . . . . . . . . . . . . . . .3-7 introduction to . . . . . . . . . . . . . . . . . . . . . . . .2-3 pointer to in TSS . . . . . . . . . . . . . . . . . . . . . .6-5 pointers to exception and interrupt handlers. . . . . . . . . . . . . . . . . . . . . . . . .5-15 segment descriptors in . . . . . . . . . . . . . . . . .3-9 segment selector field, TSS . . . . . . . . . . . .6-17 selecting with TI (table indicator) flag of segment selector . . . . . . . . . . . . . . . . . . . . . . . . . .3-8 setting up during initialization . . . . . . . . . . .8-12 task switching . . . . . . . . . . . . . . . . . . . . . . .6-10 task-gate descriptor. . . . . . . . . . . . . . . . . . . 6-8 use in...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.

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