7 3 a a accessed flag page table entry

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Unformatted text preview: register EAX, [ESI] EAX, 0F000000H; zero out all other bits except APIC ID BOOT_ID, EAX; save in memory Save the ID in the configuration RAM (optional). 7. Determine APIC ID of the AP and save it in the configuration RAM (optional). MOV EAX, BOOT_ID XOR EAX, 100000H; toggle lower bit of ID field (bit 24) MOV SECOND_ID, EAX 8. Convert the base address of the 4-KByte page for the AP’s bootup code into 8-bit vector. The 8-bit vector defines the address of a 4-KByte page in the real-address mode address space (1-MByte space). For example, a vector of 0BDH specifies a start-up memory address of 000BD000H. Use steps 9 and 10 to use the LVT APIC error handling entry to deal with unsuccessful delivery of the start-up IPI. 9. Enable the local APIC by writing to spurious vector register (SVR). This is required to do APIC error handling via the local vector table. MOV MOV OR MOV ESI, SVR ; address of SVR EAX, [ESI] EAX, APIC_ENABLED; set bit 8 to enable (0 on reset) [ESI], EAX 10. Program LVT3 (APIC error interrupt vector) of the local vector table with an 8-bit vector for handling APIC errors. MOV ESI, LVT3 MOV EAX, [ESI] AND EAX, FFFFFF00H; clear out previous vector OR EAX, 000000xxH; xx is the 8-bit vector for APIC error ; handling. MOV [ESI], EAX 11. Write APIC ICRH with address of the AP’s APIC. MOV MOV AND OR ICR_HI ; address of ICR high dword [ESI] ; get high word of ICR 0F0FFFFFFH; zero out ID Bits SECOND_ID; write ID into appropriate bits - don’t ; affect reserved bits MOV [ESI], SECOND_ID; write upgrade ID to destination field D-2 ESI, EAX, EAX, EAX, MULTIPLE-PROCESSOR (MP) BOOTUP SEQUENCE EXAMPLE 12. Initialize the memory location into which the AP will write to signal it’s presence. 13. Set the timer with an appropriate value (~100 milliseconds). 14. Write APIC ICRL to send a start-up IPI message to the AP via the APIC. MOV MOV AND OR ICR_LOW; write address of ICR low dword [ESI] ; get low dword of ICR 0FFF0F800H; zero out delivery mode and vector fields 000006xxH; 6 selects delivery mode 110 (StartUp IPI) ; xx should be vector of 4kb page as ; computed in Step 8. MOV [ESI], EAX ESI, EAX, EAX, EAX, 15. Wait for the timer interrupt or an AP signal appearing in memory. 16. If necessary, reconfigure the APIC and continue with the remaining system diagnostics as appropriate. D.2. AP’S SEQUENCE OF EVENTS FOLLOWING RECEIPT OF START-UP IPI If the AP’s APIC is to be used for symmetric multiprocessing, the AP must undertake the following steps: 1. Switch to protected mode to access the APIC addresses. 2. Initialize its local APIC by writing to bit 8 of the SVR register and programming its LVT3 for error handling. 3. Configure the APIC as appropriate. 4. Enable interrupts. 5. (Optional) Execute the CPUID instruction and write the results into the configuration RAM. 6. Write into the memory location that is being used to signal to the BSP that the AP is executing. 7. Do either of the following: — Continue execution (that is, self-configuration, MP Specification Configuration table completion). — Execute a HLT instruction and wait for an IPI from the operating system. D-3 E Programming the LINT0 and LINT1 Inputs APPENDIX E PROGRAMMING THE LINT0 AND LINT1 INPUTS The following procedure describes how to program the LINT0 and LINT1 local APIC pins on a processor after multiple processors have been booted and initialized (as described in Appendix C and Appendix D). In this example, LINT0 is programmed to be the ExtINT pin and LINT1 is programmed to be the NMI pin. E.1. CONSTANTS The following constants are defined: LVT1 LVT2 LVT3 SVR EQU 0FEE00350H EQU 0FEE00360H EQU 0FEE00370H EQU 0FEE000F0H E.2. LINT[0:1] PINS PROGRAMMING PROCEDURE Use the following to program the LINT[1:0] pins: 1. Mask 8259 interrupts. 2. Enable APIC via SVR (spurious vector register) if not already enabled. MOV MOV OR MOV ESI, SVR ; address of SVR EAX, [ESI] EAX, APIC_ENABLED; set bit 8 to enable (0 on reset) [ESI], EAX 3. Program LVT1 as an ExtINT which delivers the signal to the INTR signal of all processors cores listed in the destination as an interrupt that originated in an externally connected interrupt controller. MOV MOV AND OR LVT1 [ESI] 0FFFE58FFH; mask off bits 8-10, 12, 14 and 16 700H ; Bit 16=0 for not masked, Bit 15=0 for edge ; triggered, Bit 13=0 for high active input ; polarity, Bits 8-10 are 111b for ExtINT MOV [ESI], EAX ; Write to LVT1 ESI, EAX, EAX, EAX, E-1 PROGRAMMING THE LINT0 AND LINT1 INPUTS 4. Program LVT2 as NMI, which delivers the signal on the NMI signal of all processor cores listed in the destination. MOV MOV AND OR LVT2 [ESI] 0FFFE58FFH; mask off bits 8-10 and 15 000000400H; Bit 16=0 for not masked, Bit 15=0 edge ; triggered, Bit 13=0 for high active input ; polarity, Bits 8-10 are 100b for NMI MOV [ESI], EAX ; Write to LVT2 ;Unmask 8259 interrupts and allow NMI. ESI, EAX, EAX, EAX, E-2 INDEX Numerics 16-bit code, mixing with 32-bit code. . . . . . . . .17-1 32-bit code, mixing with 16-bit code. . . . . . ....
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

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