IntelSoftwareDevelopersManual

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Unformatted text preview: ceptions and interrupts when switching stacks . . . . . . . . . . . . . . . . . .5-10 on call to exception or interrupt handler . . .5-15 Stack underflow exception, FPU . . . . . . . . . .11-17 Stack-fault exception (#SS) . . . . . . . . . . . . . .18-35 Stacks error code pushes. . . . . . . . . . . . . . . . . . .18-33 faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-39 for privilege levels 0, 1, and 2 . . . . . . . . . . .4-21 interlevel RET/IRET from a 16-bit interrupt or call gate . . . . . . . . . . . . . . . . . . . . . . . .18-34 managment of control transfers for 16- and 32-bit procedure calls . . . . . . . . . . . . . .17-5 operation on pushes and pops . . . . . . . . .18-33 pointers to in TSS . . . . . . . . . . . . . . . . . . . . .6-6 stack switching . . . . . . . . . . . . . . . . . . . . . .4-21 usage on call to exception or interrupt handler . . . . . . . . . . . . . . . . . . . . . . . .18-33 Stepping information, following processor initialization or reset . . . . . . . . . . . . . .8-5 STI instruction . . . . . . . . . . . . . . . . . . . . . . . . . .5-9 STPCLK# pin . . . . . . . . . . . . . . . . . . . . . 5-2, 15-15 STR instruction. . . . . . . . . . . . . . . . . . . . . 3-18, 6-8 STRT instruction . . . . . . . . . . . . . . . . . . . . . . .2-20 SUB instruction . . . . . . . . . . . . . . . . . . . . . . . . .7-4 Supervisor mode description of. . . . . . . . . . . . . . . . . . . . . . . 4-31 U/S (user/supervisor) flag . . . . . . . . . . . . . 4-31 SVR (spurious-interrupt vector register), local APIC . . . . . . . . . . . . . . . . . . . . . . . . 7-34 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 instructions . . . . . . . . . . . . . . . . . . . . .2-6, 2-18 registers, introduction to . . . . . . . . . . . . . . . 2-5 segment descriptor, layout of . . . . . . . . . . . 4-3 System-management mode (see SMM) T T (debug trap) flag, TSS . . . . . . . . . . . . . .6-6, 15-2 Task gates descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 executing a task . . . . . . . . . . . . . . . . . . . . . 6-3 handling a virtual-8086 mode interrupt or exception through . . . . . . . . . . . . . . . 16-20 in IDT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 introduction to . . . . . . . . . . . . . . . . . . . .2-3, 2-4 layout of. . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 referencing of TSS descriptor . . . . . . . . . . 5-19 Task management . . . . . . . . . . . . . . . . . . . . . . 6-1 data structures . . . . . . . . . . . . . . . . . . . . . . 6-4 mechanism, description of . . . . . . . . . . . . . 6-3 Task register. . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 description of. . . . . . . . . . . . . . . . 2-11, 6-1, 6-8 initializing. . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 introduction to . . . . . . . . . . . . . . . . . . . . . . . 2-5 Task switching description of. . . . . . . . . . . . . . . . . . . . . . . . 6-3 exception condition . . . . . . . . . . . . . . . . . 15-11 operation . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 preventing recursive task switching . . . . . 6-16 T (debug trap) flag. . . . . . . . . . . . . . . . . . . . 6-6 Tasks address space. . . . . . . . . . . . . . . . . . . . . . 6-17 description of. . . . . . . . . . . . . . . . . . . . . . . . 6-1 exception-handler task . . . . . . . . . . . . . . . 5-15 executing. . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Intel 286 processor tasks . . . . . . . . . . . . 18-37 interrupt-handler task . . . . . . . . . . . . . . . . 5-15 interrupts and exceptions . . . . . . . . . . . . . 5-18 linking . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 logical address space . . . . . . . . . . . . . . . . 6-18 management . . . . . . . . . . . . . . . . . . . . . . . . 6-1 mapping to linear and physical address spaces . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 restart following an exception or interrupt . . 5-7 state (context) . . . . . . . . . . . . . . . . . . . .6-2, 6-3 structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 switching . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 task management data structures. . . . . . . . 6-4 Task-state segment (see TSS) Test registers . . . . . . . . . . . . . . . . . . . . . . . . 18-25 TF (trap) flag, EFLAGS register . 2-8, 5-18, 12-10, 15-2, 15-10, 15-12, 15-14, 16-6, 16-26 INDEX-16 INDEX TI (table indicator) flag, segment selector . . . . .3-8 Timer, local APIC . . . . . . . . . . . . . . . . . . . . . . .7-43 Time-stamp counter description of . . . . . . . . . . . . . . . . . . . . . .15-14 reading . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-22 software drivers for . . . . . . . . . . . . . . . . . .15-18 TLBs description of . . . . . . . . . . . . . . . 3-19, 9-1, 9-4 flushing . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-17 invalidating (flushing) . . . . . . . . . . . . . . . . .2-21 relationship to PGE flag . . . . . . . . . 3-27, 18-23 relationship to PSE flag . . . . . . . . . . 3-22, 9-17 TMR (Trigger Mode Register), local APIC . . . .7-30 TPR (task priority register), local APIC . . . . . .7-31 TR (trace message enable) flag, DebugCtlMSR register . . . . . . . . . . . . . . . . . . . . . .15-12 Transcendental instruction accuracy . . 18-9, 18-18 Translation lookaside buffer (see TLB) Trap gates difference between interrupt and trap gates . . . . . . . . . . . . . . . . . . . . . . . . . . .5-18 for 16-bit and 32-bit code modules . . . . . . .17-2 handling a virtual-8086 mode interrupt or exception through . . . . . . . . . . . . . . . .16-17 in IDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-13 introduction to . . . . . . . . . . . . . . . . . . . . 2-3, 2-4 layout of . . . . . . . . . . . . . . . . . . . . . . . . . . .5-13 Traps description of . . . . . . . . . . . . . . . . . . . . . . . .5-5 restarting a program or task after . . . . . . . . .5-7 TS (task switched) flag, CR0 control register . . . . . . . . . . . . . 2-14, 5-30, 6-12 TSD (time-stamp counter disable) flag, CR4 control register .2-17, 4-25, 15-15, 15-18, 18-22 TSS 16-bit TSS, structure of. . . . . . . . . . . . . . . .6-19 32-bit TSS, structure of. . . . . . . . . . . . . . . . .6-4 CR3 control register (PDBR) . . . . . . . 6-6, 6-17 description of . . . . . . . . . . . . 2-3, 2-4, 6-1, 6-4 EFLAGS register. . . . . . . . . . . . . . . . . . . . . .6-4 EIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-4 executing a task . . . . . . . . . . . . . . . . . . . . . .6-3 floating-point save area . . . . . . . . . . . . . .18-14 general-purpose registers. . . . . . . . . . . . . . .6-4 initialization for multitasking . . . . . ....
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

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