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Unformatted text preview: of SMM. This behavior is implementation specific for the Pentium® processor and is not part the Intel Architecture. 12.8. SAVING THE FPU STATE WHILE IN SMM
In some instances (for example prior to powering down system memory when entering a 0-volt suspend state), it is necessary to save the state of the FPU while in SMM. Care should be taken when performing this operation to insure that relevant FPU state information is not lost. The 12-11 SYSTEM MANAGEMENT MODE (SMM) safest way to perform this task is to place the processor in 32-bit protected mode before saving the FPU state. The reason for this is as follows. The FSAVE instruction saves the FPU context in any of four different formats, depending on which mode the processor is in when FSAVE is executed (refer to Figures 7-13 through 7-16 in the Intel Architecture Software Developer’s Manual, Volume 1). When in SMM, by default, the 16-bit real-address mode format is used (shown in Figure 7-16). If an SMI interrupt occurs while the processor is in a mode other than 16-bit real-address mode, FSAVE and FRSTOR will be unable to save and restore all the relevant FPU information, and this situation may result in a malfunction when the interrupted program is resumed. To avoid this problem, the processor should be in 32-bit protected mode when executing the FSAVE and FRSTOR instructions. The following guidelines should be used when going into protected mode from an SMI handler to save and restore the FPU state: • • Use the CPUID instruction to insure that the processor contains an FPU. Create a 32-bit code segment in SMRAM space that contains procedures or routines to save and restore the FPU using the FSAVE and FRSTOR instructions, respectively. A GDT with an appropriate code-segment descriptor (D bit is set to 1) for the 32-bit code segment must also be placed in SMRAM. Write a procedure or routine that can be called by the SMI handler to save and restore the FPU state. This procedure should do the following: — Place the processor in 32-bit protected mode as describe in Section 8.8.1., “Switching to Protected Mode” in Chapter 8, Processor Management and Initialization. — Execute a far JMP to the 32-bit code segment that contains the FPU save and restore procedures. — Place the processor back in 16-bit real-address mode before returning to the SMI handler (refer to Section 8.8.2., “Switching Back to Real-Address Mode” in Chapter 8, Processor Management and Initialization). • The SMI handler may continue to execute in protected mode after the FPU state has been saved and return safely to the interrupted program from protected mode. However, it is recommended that the handler execute primarily in 16- or 32-bit real-address mode. 12.9. SMM REVISION IDENTIFIER
The SMM revision identifier field is used to indicate the version of SMM and the SMM extensions that are supported by the processor (refer to Figure 12-2). The SMM revision identifier is written during SMM entry and can be examined in SMRAM space at offset 7EFCH. The lower word of the SMM revision identifier refers to the version of the base SMM architecture. 12-12 SYSTEM MANAGEMENT MODE (SMM) Register Offset 7EFCH
31 18 17 16 15 0 Reserved SMBASE Relocation I/O Instruction Restart Reserved SMM Revision Identifier Figure 12-2. SMM Revision Identifier The upper word of the SMM revision identifier refers to the extensions available. If the I/O instruction restart flag (bit 16) is set, the processor supports the I/O instruction restart (refer to Section 12.12., “I/O Instruction Restart”); if the SMBASE relocation flag (bit 17) is set, SMRAM base address relocation is supported (refer to Section 12.11., “SMBASE Relocation”). 12.10. AUTO HALT RESTART
If the processor is in a HALT state (due to the prior execution of a HLT instruction) when it receives an SMI, the processor records the fact in the auto HALT restart flag in the saved processor state (refer to Figure 12-3). (This flag is located at offset 7F02H and bit 0 in the state save area of the SMRAM.) If the processor sets the auto HALT restart flag upon entering SMM (indicating that the SMI occurred when the processor was in the HALT state), the SMI handler has two options: • • It can leave the auto HALT restart flag set, which instructs the RSM instruction to return program control to the HLT instruction. This option in effect causes the processor to reenter the HALT state after handling the SMI. (This is the default operation.) It can clear the auto HALT restart flag, with instructs the RSM instruction to return program control to the instruction following the HLT instruction.
15 10 Register Offset 7F02H Reserved Auto HALT Restart Figure 12-3. Auto HALT Restart Field 12-13 SYSTEM MANAGEMENT MODE (SMM) These options are summarized in Table 12-3. Note that if the processor was not in a HALT state when the SMI was received (the auto HALT restart flag is cleared), setting the flag to 1 will cause unpredictable behavior when the RSM instruction is executed.
Table 12-3. Auto HALT Restart Flag Values...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.
- Spring '10