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Unformatted text preview: rrupts originally accepted by it to other processors for service). In addition, special inter-processor interrupts (IPI) such as the start-up IPI message, can only be delivered using the ICR mechanism. ICRbased interrupts are treated as edge triggered even if programmed otherwise. Note that not all combinations of options for ICR generated interrupts are valid (refer to Table 7-2). 7-25 MULTIPLE-PROCESSOR MANAGEMENT 63 56 55 32 Destination Field Reserved 31 20 19 18 17 16 15 14 13 12 11 10 87 0 Reserved Vector Destination Shorthand 00: Dest. Field 01: Self 10: All Incl. Self 11: All Excl. Self Reserved Address: FEE0 0310H Value after Reset: 0H Delivery Mode 000: Fixed 001: Lowest Priority 010: SMI 011: Reserved 100: NMI 101: INIT 110: Start Up 111: Reserved Destination Mode 0: Physical 1: Logical Delivery Status 0: Idle 1: Send Pending Level 0 = De-assert 1 = Assert Trigger Mode 0: Edge 1: Level Figure 7-9. Interrupt Command Register (ICR) All fields of the ICR are read-write by software with the exception of the delivery status field, which is read-only. Writing to the 32-bit word that contains the interrupt vector causes the interrupt message to be sent. The ICR consists of the following fields. Vector Delivery Mode The vector identifying the interrupt being sent. The localAPIC register addresses are summarized in Table 7-1. Specifies how the APICs listed in the destination field should act upon reception of the interrupt. Note that all interprocessor interrupts behave as edge triggered interrupts (except for INIT level de-assert message) even if they are programmed as level triggered interrupts. 000 (Fixed) Deliver the interrupt to all processors listed in the destination field according to the information provided in the ICR. The fixed interrupt is treated as 7-26 MULTIPLE-PROCESSOR MANAGEMENT an edge-triggered interrupt even if programmed otherwise. 001 (Lowest Priority) Same as fixed mode, except that the interrupt is delivered to the processor executing at the lowest priority among the set of processors listed in the destination. 010 (SMI) 011 (Reserved) 100 (NMI) Delivers the interrupt as an NMI interrupt to all processors listed in the destination field. The vector information is ignored. NMI is treated as an edge triggered interrupt even if programmed otherwise. Delivers the interrupt as an INIT signal to all processors listed in the destination field. As a result, all addressed APICs will assume their INIT state. As in the case of NMI, the vector information is ignored, and INIT is treated as an edge triggered interrupt even if programmed otherwise. Only the edge trigger mode is allowed. The vector field must be programmed to 00B. 101 (INIT) 101 (INIT Level De-assert) (The trigger mode must also be set to 1 and level mode to 0.) Sends a synchronization message to all APIC agents to set their arbitration IDs to the values of their APIC IDs. Note that the INIT interrupt is sent to all agents, regardless of the destination field value. However, at least one valid destination processor should be specified. For future compatibility, the software is requested to use a broadcast-to-all (“all-incl-self” shorthand, as described below). 110 (Start-Up) Sends a special message between processors in a multiple-processor system. For details refer to the Pentium® Pro Family Developer’s Manual, Volume 1. The Vector information contains the startup address for the multiple-processor boot-up protocol. Start-up is treated as an edge triggered interrupt even if programmed otherwise. Note that interrupts are not automatically retried by the source APIC upon failure in delivery of the message. It is up to the software to decide whether a 7-27 MULTIPLE-PROCESSOR MANAGEMENT retry is needed in the case of failure, and issue a retry message accordingly. Destination Mode Delivery Status Selects either (0) physical or (1) logical destination mode. Indicates the delivery status: 0 (Idle) There is currently no activity for this interrupt, or the previous interrupt from this source has completed. 1 (Send Pending) Indicates that the interrupt transmission has started, but has not yet been completely accepted. Level Trigger Mode Destination Shorthand Indicates whether a shorthand notation is used to specify the destination of the interrupt and, if so, which shorthand is used. Destination shorthands do not use the 8-bit destination field, and can be sent by software using a single write to the lower 32-bit part of the APIC interrupt command register. Shorthands are defined for the following cases: software self interrupt, interrupt to all processors in the system including the sender, interrupts to all processors in the system excluding the sender. 00: (destination field, no shorthand) The destination is specified in bits 56 through 63 of the ICR. 01: (self) The current APIC is the single destination of the interrupt. This is useful for software self interrupts. The destination field is ignored. Refer to Table 7-2 for description of supported modes. Note that self interrupts do not generate bus messages. For INIT level de-assert delivery mode the level is 0. For all other...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.
- Spring '10