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Unformatted text preview: riate to load on a processor. The information encoded within this field exactly corresponds to the bit representations returned by the CPUID instruction.
Checksum of update data and header. Used to verify the integrity of the update header and data. Checksum is correct when the summation of the 512 double words of the update result in the value zero. Version number of the loader program needed to correctly load this update. The initial version is 00000001h. Platform type information is encoded in the lower 8 bits of this 4-byte field. Each bit represents a particular platform type for a given CPUID. The BIOS uses the Processor Flags field in conjunction with the platform ID bits in MSR (17h) to determine whether or not an update is appropriate to load on a processor. Reserved Fields for future expansion. Update data. Checksum 16 4 Loader Revision 20 4 Processor Flags 24 4 Reserved Update Data 28 48 20 2000 8-34 PROCESSOR MANAGEMENT AND INITIALIZATION 32 24 16 8 0 Update Data (2000 Bytes) Reserved (20 Bytes) Processor Flags
Reserved: 24 P7: I P6: I P5: I P4: I P3: I P2: I P1: I Loader Revision Checksum Processor
Reserved: 18 ProcType: 2 Family: 4 Model: 4 Stepping: 4 Date
Month: 8 Day: 8 Year: 16 Update Revision Header Revision
32 24 16 8 0 Figure 8-8. Format of the Microcode Update Data Block 8.10.2. Microcode Update Loader
This section describes the update loader used to load a microcode update into a P6 family processor. It also discusses the requirements placed upon the BIOS to ensure proper loading of an update. The update loader contains the minimal instructions needed to load an update. The specific instruction sequence that is required to load an update is dependent upon the loader revision field contained within the update header. The revision of the update loader is expected to change very infrequently, potentially only when new processor models are introduced. 8-35 PROCESSOR MANAGEMENT AND INITIALIZATION The code below represents the update loader with a loader revision of 00000001h:
mov ecx,79h ; MSR to read in ECX xor eax,eax ; clear EAX xor ebx,ebx ; clear EBX movax,cs ; Segment of microcode update shl eax,4 movbx,offset Update ; Offset of microcode update addeax,ebx ; Linear Address of Update in EAX addeax,48d ; Offset of the Update Data within the Update xor edx,edx ; Zero in EDX WRMSR ; microcode update trigger 220.127.116.11. UPDATE LOADING PROCEDURE The simple loader previously described assumes that Update is the address of a microcode update (header and data) embedded within the code segment of the BIOS. It also assumes that the processor is operating in real mode. The data may reside anywhere in memory that is accessible by the processor within its current operating mode (real, protected). Before the BIOS executes the microcode update trigger (WRMSR) instruction the following must be true: • • • • • • • • EAX contains the linear address of the start of the update data EDX contains zero ECX contains 79h Other requirements to keep in mind are: The microcode update must be loaded to the processor early on in the POST, and always prior to the initialization of the P6 family processors L2 cache controller. If the update is loaded while the processor is in real mode, then the update data may not cross a segment boundary. If the update is loaded while the processor is in real mode, then the update data may not exceed a segment limit. If paging is enabled, pages that are currently present must map the update data. The microcode update data does not require any particular byte or word boundary alignment. HARD RESETS IN UPDATE LOADING 18.104.22.168. The effects of a loaded update are cleared from the processor upon a hard reset. Therefore, each time a hard reset is asserted during the BIOS POST, the update must be reloaded on all processors that observed the reset. The effects of a loaded update are, however, maintained across a processor INIT. There are no side effects caused by loading an update into a processor multiple times. 8-36 PROCESSOR MANAGEMENT AND INITIALIZATION 22.214.171.124. UPDATE IN A MULTIPROCESSOR SYSTEM A multiprocessor (MP) system requires loading each processor with update data appropriate for its CPUID and platform ID bits. The BIOS is responsible for ensuring that this requirement is met, and that the loader is located in a module that is executed by all processors in the system. If a system design permits multiple steppings of P6 family processors to exist concurrently, then the BIOS must verify each individual processor against the update header information to ensure appropriate loading. Given these considerations, it is most practical to load the update during MP initialization. 126.96.36.199. UPDATE LOADER ENHANCEMENTS The update loader presented in Section 188.8.131.52., “Update Loading Procedure” is a minimal implementation that can be enhanced to provide additional functionality and features. Some potential enhancements are described below: • The BIOS can incorporate multiple updates to support multiple steppings of the P6 family...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.
- Spring '10