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Unformatted text preview: re performed with 32-bit CALL instructions (by default, because the D flag for the interface procedure’s code segment is set), and returns from the called procedures to the interface procedure are performed with 32-bit RET instructions (also by default). Calls from 32-bit procedures to 16-bit procedures. Calls to the interface procedure from a 32-bit code segment are made with 32-bit CALL instructions (by default), and returns to the calling procedure from the interface procedure are made with 32-bit RET instructions (also by default). Calls from the interface procedure to 16-bit procedures require the CALL instructions to have the operand-size prefixes, and returns from the called procedures to the interface procedure are performed with 16-bit RET instructions (by default). • 17-9 MIXING 16-BIT AND 32-BIT CODE 17-10 18
Intel Architecture Compatibility CHAPTER 18 INTEL ARCHITECTURE COMPATIBILITY
All Intel Architecture processors are binary compatible. Compatibility means that, within certain limited constraints, programs that execute on previous generations of Intel Architecture processors will produce identical results when executed on later Intel Architecture processors. The compatibility constraints and any implementation differences between the Intel Architecture processors are described in this chapter. Each new Intel Architecture processor has enhanced the software visible architecture from that found in earlier Intel Architecture processors. Those enhancements have been defined with consideration for compatibility with previous and future processors. This chapter also summarizes the compatibility considerations for those extensions. 18.1. INTEL ARCHITECTURE FAMILIES AND CATEGORIES
Intel Architecture processors are referred to in several different ways in this chapter, depending on the type of compatibility information being related, as described in the following: • • • • Intel Architecture Processors—All the Intel processors based on the Intel Architecture, which include the 8086/88, Intel 286, Intel386™, Intel486™, Pentium®, and P6 family processors. 32-bit Processors—All the Intel Architecture processors that use a 32-bit architecture, which include the Intel386™, Intel486™, Pentium®, and P6 family processors. 16-bit Processors—All the Intel Architecture processors that use a 16-bit architecture, which include the 8086/88 and Intel 286 processors. P6 Family Processors—All the Intel Architecture processors that are based on the P6 family micro-architecture, which include the Pentium® Pro, Pentium® II, Pentium® III and future P6 family processors. 18.2. RESERVED BITS
Throughout this manual, certain bits are marked as reserved in many register and memory layout descriptions. When bits are marked as undefined or reserved, it is essential for compatibility with future processors that software treat these bits as having a future, though unknown effect. Software should follow these guidelines in dealing with reserved bits: • • Do not depend on the states of any reserved bits when testing the values of registers or memory locations that contain such bits. Mask out the reserved bits before testing. Do not depend on the states of any reserved bits when storing them to memory or to a register. 18-1 INTEL ARCHITECTURE COMPATIBILITY • • Do not depend on the ability to retain information written into any reserved bits. When loading a register, always load the reserved bits with the values indicated in the documentation, if any, or reload them with values previously read from the same register. Software written for existing Intel Architecture processor that handles reserved bits correctly will port to future Intel Architecture processors without generating protection exceptions. 18.3. ENABLING NEW FUNCTIONS AND MODES
Most of the new control functions defined for the P6 family and Pentium® processors are enabled by new mode flags in the control registers (primarily register CR4). This register is undefined for Intel Architecture processors earlier than the Pentium ® processor. Attempting to access this register with an Intel486™ or earlier Intel Architecture processor results in an invalid-opcode exception (#UD). Consequently, programs that execute correctly on the Intel486™ or earlier Intel Architecture processor cannot erroneously enable these functions. Attempting to set a reserved bit in register CR4 to a value other than its original value results in a general-protection exception (#GP). So, programs that execute on the P6 family and Pentium® processors cannot erroneously enable functions that may be implemented in future Intel Architecture processors. The P6 family and Pentium® processors do not check for attempts to set reserved bits in modelspecific registers. It is the obligation of the software writer to enforce this discipline. These reserved bits may be used in future Intel processors. 18.4. DETECTING THE PRESENCE OF NEW FEATURES THROUGH SOFTWARE
Software can check for the presence of new architectural features and exte...
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- Spring '10