IntelSoftwareDevelopersManual

18 8 msrs description of

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: . . . . . . . .7-15 Local APIC version register . . . . . . . . . . . . . . .7-36 Local descriptor table register (see LDTR) Local descriptor table (see LDT) Local vector table (LVT), local APIC . . . . . . . .7-23 LOCK prefix . 2-22, 5-28, 7-2, 7-3, 7-4, 7-9, 18-37 Locked (atomic) operations automatic bus locking . . . . . . . . . . . . . . . . . .7-3 bus locking . . . . . . . . . . . . . . . . . . . . . . . . . .7-3 effects of a locked operation on internal processor caches . . . . . . . . . . . . . . . . . .7-6 loading a segment descriptor . . . . . . . . . .18-24 on Intel Architecture processors . . . . . . . .18-37 overview of . . . . . . . . . . . . . . . . . . . . . . . . . .7-2 software-controlled bus locking . . . . . . . . . .7-4 LOCK# signal . . . . . . . . . . . 2-22, 7-2, 7-3, 7-4, 7-6 Logical address space, of task. . . . . . . . . . . . .6-18 Logical address, description of. . . . . . . . . . . . . .3-6 Logical destination mode, local APIC. . . . . . . .7-20 LSL instruction . . . . . . . . . . . . . . . . . . . . 2-20, 4-28 LSS instruction . . . . . . . . . . . . . . . . . . . . . 3-9, 4-10 LTR instruction . . . . . . . 2-20, 4-25, 6-8, 7-12, 8-13 LVT (local vector table), local APIC . . . . . . . . .7-23 M Machine-check architecture availability of machine-check architecture and exception . . . . . . . . . . . . . . . . . . . . . . . 13-7 compatibility with Pentium processor implementation . . . . . . . . . . . . . . . . . . 13-1 error codes, compound . . . . . . . . . . . . . . . 13-9 error codes, interpreting . . . . . . . . . . . . . . 13-8 error codes, simple . . . . . . . . . . . . . . . . . . 13-9 error-reporting MSRs . . . . . . . . . . . . . . . . 13-4 first introduced. . . . . . . . . . . . . . . . . . . . . 18-27 global MSRs . . . . . . . . . . . . . . . . . . . . . . . 13-2 guidelines for writing machine-check software . . . . . . . . . . . . . . . . . . . . . . . 13-14 initialization of . . . . . . . . . . . . . . . . . . . . . . 13-7 introduction of in Intel Architecture processors . . . . . . . . . . . . . . . . . . . . . 18-39 logging correctable machine-check errors 13-16 machine-check error codes, external bus errors . . . . . . . . . . . . . . . . . . . . . . . . . 13-11 machine-check exception handler. . . . . . 13-14 MCG_CAP MSR . . . . . . . . . . . . . . . . . . . . 13-2 MCG_CTL MSR . . . . . . . . . . . . . . . . . . . . 13-4 MCi_ADDR MSRs. . . . . . . . . . . . . . . . . . . 13-6 MCi_CTL MSRs . . . . . . . . . . . . . . . . . . . . 13-4 MCi_MISC MSRs . . . . . . . . . . . . . . . . . . . 13-7 MCi_STATUS MSRs. . . . . . . . . . . . . . . . . 13-5 MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 P5_MC_ADDR MSR . . . . . . . . . . . . . . . . . 13-7 P5_MC_TYPE MSR . . . . . . . . . . . . . . . . . 13-7 Pentium processor machine-check exception handling . . . . . . . . . . . . . . . . . . . . . . . 13-16 Pentium processor style error reporting . . 13-7 Machine-check exception (#MC) 5-52, 13-1, 13-7, 13-14, 18-26, 18-39 Maskable hardware interrupts delivered with local APIC . . . . . . . . . . . . . 7-23 description of. . . . . . . . . . . . . . . . . . . . . . . . 5-2 handling with virtual interrupt mechanism 16-20 masking. . . . . . . . . . . . . . . . . . . . . . . . .2-8, 5-8 Masked responses to denormal operand exception. . . . . . . . 11-19 to FPU stack overflow or underflow exception . . . . . . . . . . . . . . . . . . . . . . 11-17 to inexact result (precision) exception. . . 11-21 to numeric overflow exception. . . . . . . . . 11-20 MCA (machine-check architecture) flag, CPUID instruction . . . . . . . . . . . . . . . . . . . . 13-7 MCE (machine-check enable) flag, CR4 control register . . . . . . . . . . . . . . . . .2-17, 18-22 MCE (machine-check exception) flag, CPUID instruction . . . . . . . . . . . . . . . . . . . . 13-7 MCG_CAP MSR. . . . . . . . . . . . . . . . . .13-2, 13-15 MCG_CTL MSR . . . . . . . . . . . . . . . . . . . . . . . 13-4 MCG_STATUS MSR . . . . . . . . . . . . .13-15, 13-17 MCi_ADDR MSRs . . . . . . . . . . . . . . . . . . . . 13-17 MCi_CTL MSRs . . . . . . . . . . . . . . . . . . . . . . . 13-4 INDEX-10 INDEX MCi_MISC MSRs . . . . . . . . . . . . . . . . . 13-7, 13-17 MCi_STATUS MSRs . . . . . . . . 13-5, 13-15, 13-17 MDA (message destination address), local APIC. . . . . . . . . . . . . . . . . . . . . . . . .7-20 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1 Memory management introduction to . . . . . . . . . . . . . . . . . . . . . . . .2-5 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1 paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1 segmentation . . . . . . . . . . . . . . . . . . . . . . . .3-1 Memory ordering in Intel Architecture processors . . . . . . . .18-36 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-6 processor ordering . . . . . . . . . . . . . . . . . . . ....
View Full Document

This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.

Ask a homework question - tutors are online