Unformatted text preview: s in register CR0 are interpreted as shown in Table 18-2.
Table 18-2. EM and MP Flag Interpretation
EM 0 0 1 1 MP 0 1 0 1 Interpretation Floating-point instructions are passed to FPU; WAIT/FWAIT and other waiting-type instructions ignore TS. Floating-point instructions are passed to FPU; WAIT/FWAIT and other waiting-type instructions test TS. Floating-point instructions trap to emulator; WAIT/FWAIT and other waiting-type instructions ignore TS. Floating-point instructions trap to emulator; WAIT/FWAIT and other waiting-type instructions test TS. Following is an example code sequence to initialize the system and check for the presence of Intel486™ SX processor/Intel 487 SX math coprocessor.
fninit fstcw mem_loc mov ax, mem_loc cmp ax, 037fh jz Intel487_SX_Math_CoProcessor_present;ax=037fh jmp Intel486_SX_microprocessor_present;ax=ffffh If the Intel 487 SX math coprocessor is not present, the following code can be run to set the CR0 register for the Intel486™ SX processor. 18-20 INTEL ARCHITECTURE COMPATIBILITY mov eax, cr0 and eax, fffffffdh ;make MP=0 or eax, 0024h ;make EM=1, NE=1 mov cr0, eax This initialization will cause any floating-point instruction to generate a device not available exception (#NH), interrupt 7. The software emulation will then take control to execute these instructions. This code is not required if an Intel 487 SX math coprocessor is present in the system. In that case, the typical initialization routine for the Intel486™ SX microprocessor will be adequate. Also, when designing an Intel486™ SX processor based system with an Intel 487 SX math coprocessor, timing loops should be independent of clock speed and clocks per instruction. One way to attain this is to implement these loops in hardware and not in software (for example, BIOS). 18.15. CONTROL REGISTERS
The following sections identify the new control registers and control register flags and fields that were introduced to the 32-bit Intel Architecture in various processor families. Refer to Figure 2-5 in Chapter 2, System Architecture Overview for the location of these flags and fields in the control registers. The Pentium® III processor introduced one new control flag in control register CR4: • • OSXMMEXCPT (bit 10)—The OS will set this bit if it supports unmasked SIMD floatingpoint exceptions. The Pentium® II processor introduced one new control flag in control register CR4: OSFXSR (bit 9)—The OS supports saving and restoring the Pentium® III processor state during context switches. The Pentium® Pro processor introduced three new control flags in control register CR4: • PAE (bit 5)—Physical address extension. Enables paging mechanism to reference 36-bit physical addresses when set; restricts physical addresses to 32 bits when clear (refer to Section 188.8.131.52., “Physical Memory Addressing Extension” in Chapter 18, Intel Architecture Compatibility). PGE (bit 7)—Page global enable. Inhibits flushing of frequently-used or shared pages on task switches (refer to Section 184.108.40.206., “Global Pages” in Chapter 18, Intel Architecture Compatibility). PCE (bit 8)—Performance-monitoring counter enable. Enables execution of the RDPMC instruction at any protection level. • • The content of CR4 is 0H following a hardware reset. 18-21 INTEL ARCHITECTURE COMPATIBILITY Control register CR4 was introduced in the Pentium® processor. This register contains flags that enable certain new extensions provided in the Pentium® processor: • • • • VME—Virtual-8086 mode extensions. Enables support for a virtual interrupt flag in virtual-8086 mode (refer to Section 16.3., “Interrupt and Exception Handling in Virtual8086 Mode” in Chapter 16, 8086 Emulation). PVI—Protected-mode virtual interrupts. Enables support for a virtual interrupt flag in protected mode (refer to Section 16.4., “Protected-Mode Virtual Interrupts” in Chapter 16, 8086 Emulation). TSD—Time-stamp disable. Restricts the execution of the RDTSC instruction to procedures running at privileged level 0. DE—Debugging extensions. Causes an undefined opcode (#UD) exception to be generated when debug registers DR4 and DR5 are references for improved performance (refer to Section 15.2.2., “Debug Registers DR4 and DR5” in Chapter 15, Debugging and Performance Monitoring). PSE—Page size extensions. Enables 4-MByte pages when set (refer to Section 3.6.1., “Paging Options” in Chapter 3, Protected-Mode Memory Management). MCE—Machine-check enable. Enables the machine-check exception, allowing exception handling for certain hardware error conditions (refer to Chapter 13, Machine-Check Architecture). • • The Intel486™ processor introduced five new flags in control register CR0: • • • • • NE—Numeric error. Enables the normal mechanism for reporting floating-point numeric errors. WP—Write protect. Write-protects user-level pages against supervisor-mode accesses. AM—Alignment mask. Controls whether alignment checking is performed. Operates in conjunction with the AC (Alignmen...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.
- Spring '10