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Unformatted text preview: recommended). 18-28 INTEL ARCHITECTURE COMPATIBILITY 18.21.4. Using A 16-Bit TSS with 32-Bit Constructs
Task switches using 16-bit TSSs should be used only for pure 16-bit code. Any new code written using 32-bit constructs (operands, addressing, or the upper word of the EFLAGS register) should use only 32-bit TSSs. This is due to the fact that the 32-bit processors do not save the upper 16 bits of EFLAGS to a 16-bit TSS. A task switch back to a 16-bit task that was executing in virtual mode will never re-enable the virtual mode, as this flag was not saved in the upper half of the EFLAGS value in the TSS. Therefore, it is strongly recommended that any code using 32-bit constructs use a 32-bit TSS to ensure correct behavior in a multitasking environment. 18.21.5. Differences in I/O Map Base Addresses
The Intel486™ processor considers the TSS segment to be a 16-bit segment and wraps around the 64K boundary. Any I/O accesses check for permission to access this I/O address at the I/O base address plus the I/O offset. If the I/O map base address exceeds the specified limit of 0DFFFH, an I/O access will wrap around and obtain the permission for the I/O address at an incorrect location within the TSS. A TSS limit violation does not occur in this situation on the Intel486™ processor. However, the P6 family and Pentium® processors consider the TSS to be a 32-bit segment and a limit violation occurs when the I/O base address plus the I/O offset is greater than the TSS limit. By following the recommended specification for the I/O base address to be less than 0DFFFH, the Intel486™ processor will not wrap around and access incorrect locations within the TSS for I/O port validation and the P6 family and Pentium® processors will not experience general-protection exceptions (#GP). Figure 18-1 demonstrates the different areas accessed by the Intel486™ and the P6 family and Pentium® processors. 18-29 INTEL ARCHITECTURE COMPATIBILITY Intel486™ Processor P6 family and Pentium® Processors
FFFFH + 10H = Outside Segment for I/O Validation FFFFH
I/O Map Base Addres FFFFH
I/O Map Base Addres FFFFH FFFFH FFFFH + 10H = FH for I/O Validation 0H
I/O access at port 10H checks bitmap at I/O map base address FFFFH + 10H = offset 10H. Offset FH from beginning of TSS segment results because wraparound occurs. 0H
I/O access at port 10H checks bitmap at I/O address FFFFH + 10H, which exceeds segment limit. Wrap around does not occur, general-protection exception (#GP) occurs. Figure 18-1. I/O Map Base Address Differences 18.22. CACHE MANAGEMENT
The P6 family processors include two levels of internal caches: L1 (level 1) and L2 (level 2). The L1 cache is divided into an instruction cache and a data cache; the L2 cache is a generalpurpose cache. Refer to Section 9.1., “Internal Caches, TLBs, and Buffers”, in Chapter 9, Memory Cache Control, for a description of these caches. (Note that although the Pentium® II processor L2 cache is physically located on a separate chip in the cassette, it is considered an internal cache.) The Pentium® processor includes separate level 1 instruction and data caches. The data cache supports a writeback (or alternatively write-through, on a line by line basis) policy for memory updates. Refer to the Pentium® Processor Data Book for more information about the organization and operation of the Pentium® processor caches. The Intel486™ processor includes a single level 1 cache for both instructions and data. The meaning of the CD and NW flags in control register CR0 have been redefined for the P6 family and Pentium® processors. For these processors, the recommended value (00B) enables writeback for the data cache of the Pentium® processor and for the L1 data cache and L2 cache of the P6 family processors. In the Intel486™ processor, setting these flags to (00B) enables write-through for the cache. External system hardware can force the Pentium® processor to disable caching or to use the write-through cache policy should that be required. Refer to the Pentium® Processor Data Book 18-30 INTEL ARCHITECTURE COMPATIBILITY for more information about hardware control of the Pentium® processor caches. In the P6 family processors, the MTRRs can be used to override the CD and NW flags (refer to Table 9-6, in Chapter 9, Memory Cache Control). The P6 family and Pentium® processors support page-level cache management in the same manner as the Intel486™ processor by using the PCD and PWT flags in control register CR3, the page-directory entries, and the page-table entries. The Intel486™ processor, however, is not affected by the state of the PWT flag since the internal cache of the Intel486™ processor is a write-through cache. 18.22.1. Self-Modifying Code with Cache Enabled
On the Intel486™ processor, a write to an instruction in the cache will modify it in both the cache and memory. If the instruction was prefetched before the write, however, the old version of the instruction could be the one executed. To prevent this problem, it is necessary...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.
- Spring '10