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Unformatted text preview: s (MSRs)” in Chapter 8, Processor Management and Initialization for more information about the MSRs and Appendix B, Model-Specific Registers for a complete list of the MSRs. Most systems restrict access to all system registers (other than the EFLAGS register) by application programs. Systems can be designed, however, where all programs and procedures run at the most privileged level (privilege level 0), in which case application programs are allowed to modify the system registers. 2.1.7. Other System Resources Besides the system registers and data structures described in the previous sections, the system architecture provides the following additional resources: • • • Operating system instructions (refer to Section 2.6., “System Instruction Summary”). Performance-monitoring counters (not shown in Figure 2-1). Internal caches and buffers (not shown in Figure 2-1). The performance-monitoring counters are event counters that can be programmed to count processor events such as the number of instructions decoded, the number of interrupts received, or the number of cache loads. Refer to Section 15.6., “Performance-Monitoring Counters”, in Chapter 15, Debugging and Performance Monitoring , for more information about these counters. The processor provides several internal caches and buffers. The caches are used to store both data and instructions. The buffers are used to store things like decoded addresses to system and application segments and write operations waiting to be performed. Refer to Chapter 9, Memory Cache Control, for a detailed discussion of the processor’s caches and buffers. 2.2. MODES OF OPERATION The Intel Architecture supports three operating modes and one quasi-operating mode: • • • Protected mode. This is the native operating mode of the processor. In this mode all instructions and architectural features are available, providing the highest performance and capability. This is the recommended mode for all new applications and operating systems. Real-address mode. This operating mode provides the programming environment of the Intel 8086 processor, with a few extensions (such as the ability to switch to protected or system management mode). System management mode (SMM). The system management mode (SMM) is a standard architectural feature in all Intel Architecture processors, beginning with the Intel386™ SL processor. This mode provides an operating system or executive with a transparent mechanism for implementing power management and OEM differentiation features. SMM is entered through activation of an external system interrupt pin (SMI#), which generates a 2-6 SYSTEM ARCHITECTURE OVERVIEW system management interrupt (SMI). In SMM, the processor switches to a separate address space while saving the context of the currently running program or task. SMM-specific code may then be executed transparently. Upon returning from SMM, the processor is placed back into its state prior to the SMI. • Virtual-8086 mode. In protected mode, the processor supports a quasi-operating mode known as virtual-8086 mode. This mode allows the processor to execute 8086 software in a protected, multitasking environment. Figure 2-2 shows how the processor moves among these operating modes. Real-Address Mode Reset or PE=0 PE=1 Reset or RSM SMI# SMI# Reset Protected Mode RSM VM=0 VM=1 SMI# Virtual-8086 Mode RSM System Management Mode Figure 2-2. Transitions Among the Processor’s Operating Modes The processor is placed in real-address mode following power-up or a reset. Thereafter, the PE flag in control register CR0 controls whether the processor is operating in real-address or protected mode (refer to Section 2.5., “Control Registers”). Refer to Section 8.8., “Mode Switching” in Chapter 8, Processor Management and Initialization for detailed information on switching between real-address mode and protected mode. The VM flag in the EFLAGS register determines whether the processor is operating in protected mode or virtual-8086 mode. Transitions between protected mode and virtual-8086 mode are generally carried out as part of a task switch or a return from an interrupt or exception handler (refer to Section 16.2.5., “Entering Virtual-8086 Mode” in Chapter 16, 8086 Emulation). The processor switches to SMM whenever it receives an SMI while the processor is in realaddress, protected, or virtual-8086 modes. Upon execution of the RSM instruction, the processor always returns to the mode it was in when the SMI occurred. 2-7 SYSTEM ARCHITECTURE OVERVIEW 2.3. SYSTEM FLAGS AND FIELDS IN THE EFLAGS REGISTER The system flags and IOPL field of the EFLAGS register control I/O, maskable hardware interrupts, debugging, task switching, and the virtual-8086 mode (refer to Figure 2-3). Only privileged code (typically operating system or executive code) should be allowed to modify these bits. The functions of the system flags and IOPL are as follows: TF Trap (bit 8). Set to enable single-step mode for debugging; clear to disable single-step mode. In single-step mode, the processor generates a debug exception after each instruction, which allows the execution state of a program to be inspected after each instruction. If an application program sets the TF flag using a POPF, POPFD, or IRE...
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