IntelSoftwareDevelopersManual

3 system flags and fields in the eflags register in

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Unformatted text preview: dle an interrupt or exception generated in virtual-8086 mode. 16.2.7. Sensitive Instructions When an Intel Architecture processor is running in virtual-8086 mode, the CLI, STI, PUSHF, POPF, INT n, and IRET instructions are sensitive to IOPL. The IN, INS, OUT, and OUTS instructions, which are sensitive to IOPL in protected mode, are not sensitive in virtual-8086 mode. The CPL is always 3 while running in virtual-8086 mode; if the IOPL is less than 3, an attempt to use the IOPL-sensitive instructions listed above triggers a general-protection exception (#GP). These instructions are sensitive to IOPL to give the virtual-8086 monitor a chance to emulate the facilities they affect. 16.2.8. Virtual-8086 Mode I/O Many 8086 programs written for nonmultitasking systems directly access I/O ports. This practice may cause problems in a multitasking environment. If more than one program accesses the same port, they may interfere with each other. Most multitasking systems require application programs to access I/O ports through the operating system. This results in simplified, centralized control. The processor provides I/O protection for creating I/O that is compatible with the environment and transparent to 8086 programs. Designers may take any of several possible approaches to protecting I/O ports: • • • • Protect the I/O address space and generate exceptions for all attempts to perform I/O directly. Let the 8086 program perform I/O directly. Generate exceptions on attempts to access specific I/O ports. Generate exceptions on attempts to access specific memory-mapped I/O ports. The method of controlling access to I/O ports depends upon whether they are I/O-port mapped or memory mapped. 16-14 8086 EMULATION 16.2.8.1. I/O-PORT-MAPPED I/O The I/O permission bit map in the TSS can be used to generate exceptions on attempts to access specific I/O port addresses. The I/O permission bit map of each virtual-8086-mode task determines which I/O addresses generate exceptions for that task. Because each task may have a different I/O permission bit map, the addresses that generate exceptions for one task may be different from the addresses for another task. This differs from protected mode in which, if the CPL is less than or equal to the IOPL, I/O access is allowed without checking the I/O permission bit map. Refer to Chapter 9, Input/Output, in the Intel Architecture Software Developer’s Manual, Volume 1, for more information about the I/O permission bit map. 16.2.8.2. MEMORY-MAPPED I/O In systems which use memory-mapped I/O, the paging facilities of the processor can be used to generate exceptions for attempts to access I/O ports. The virtual-8086 monitor may use paging to control memory-mapped I/O in these ways: • • Map part of the linear address space of each task that needs to perform I/O to the physical address space where I/O ports are placed. By putting the I/O ports at different addresses (in different pages), the paging mechanism can enforce isolation between tasks. Map part of the linear address space to pages that are not-present. This generates an exception whenever a task attempts to perform I/O to those pages. System software then can interpret the I/O operation being attempted. Software emulation of the I/O space may require too much operating system intervention under some conditions. In these cases, it may be possible to generate an exception for only the first attempt to access I/O. The system software then may determine whether a program can be given exclusive control of I/O temporarily, the protection of the I/O space may be lifted, and the program allowed to run at full speed. 16.2.8.3. SPECIAL I/O BUFFERS Buffers of intelligent controllers (for example, a bit-mapped frame buffer) also can be emulated using page mapping. The linear space for the buffer can be mapped to a different physical space for each virtual-8086-mode task. The virtual-8086 monitor then can control which virtual buffer to copy onto the real buffer in the physical address space. 16.3. INTERRUPT AND EXCEPTION HANDLING IN VIRTUAL-8086 MODE When the processor receives an interrupt or detects an exception condition while in virtual-8086 mode, it invokes an interrupt or exception handler, just as it does in protected or real-address mode. The interrupt or exception handler that is invoked and the mechanism used to invoke it depends on the class of interrupt or exception that has been detected or generated and the state of various system flags and fields. 16-15 8086 EMULATION In virtual-8086 mode, the interrupts and exceptions are divided into three classes for the purposes of handling: • Class 1—All processor-generated exceptions and all hardware interrupts, including the NMI interrupt and the hardware interrupts sent to the processor’s external interrupt delivery pins. All class 1 exceptions and interrupts are handled by the protected-mode exception and interrupt handlers. Class 2—Special case for maskable hardware interrupts (Section 5.1.1.2., “Maskable Hardware Interrupts”, in Chapter 5, Interrupt and Exception Handling) when the virtual mode e...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.

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