Unformatted text preview: • Stop counters. Read the event counters. Read the time-stamp counter. The event monitor feature determination procedure must determine whether the current processor supports the performance-monitoring counters and time-stamp counter. This procedure compares the family and model of the processor returned by the CPUID instruction with those of processors known to support performance monitoring. (The Pentium® and P6 family processors support performance counters.) The procedure also checks the MSR and TSC flags returned to register EDX by the CPUID instruction to determine if the MSRs and the RDTSC instruction are supported. The initialize and start counters procedure sets the PerfEvtSel0 and/or PerfEvtSel1 MSRs for the events to be counted and the method used to count them and initializes the counter MSRs (PerfCtr0 and PerfCtr1) to starting counts. The stop counters procedure stops the performance counters. (Refer to Section 220.127.116.11., “Starting and Stopping the Performance-Monitoring Counters” for more information about starting and stopping the counters.) The read counters procedure reads the values in the PerfCtr0 and PerfCtr1 MSRs, and a read time-stamp counter procedure reads the time-stamp counter. These procedures would be provided in lieu of enabling the RDTSC and RDPMC instructions that allow application code to read the counters. 15.6.2. Monitoring Counter Overflow
The P6 family processors provide the option of generating a local APIC interrupt when a performance-monitoring counter overflows. This mechanism is enabled by setting the interrupt enable flag in either the PerfEvtSel0 or the PerfEvtSel1 MSR. The primary use of this option is for statistical performance sampling. To use this option, the operating system should do the following things on the processor for which performance events are required to be monitored: • • • • Provide an interrupt vector for handling the counter-overflow interrupt. Initialize the APIC PERF local vector entry to enable handling of performance-monitor counter overflow events. Provide an entry in the IDT that points to a stub exception handler that returns without executing any instructions. Provide an event monitor driver that provides the actual interrupt handler and modifies the reserved IDT entry to point to its interrupt routine. When interrupted by a counter overflow, the interrupt handler needs to perform the following actions: • Save the instruction pointer (EIP register), code-segment selector, TSS segment selector, counter values and other relevant information at the time of the interrupt. 15-19 DEBUGGING AND PERFORMANCE MONITORING • Reset the counter to its initial setting and return from the interrupt. An event monitor application utility or another application program can read the information collected for analysis of the performance of the profiled application. 15.6.3. Pentium® Processor Performance-Monitoring Counters
The Pentium® processor provides two 40-bit performance counters, which can be used either to count events or measure duration. The performance-monitoring counters are supported by three MSRs: the control and event select MSR (CESR) and the performance counter MSRs (CTR0 and CTR1). These registers can be read from and written to using the RDMSR and WRMSR instructions, respectively. They can be accessed using these instructions only when operating at privilege level 0. Each counter has an associated external pin (PM0/BP0 and PM1/BP1), which can be used to indicate the state of the counter to external hardware.
NOTE The CESR, CTR0, and CTR1 MSRs and the events listed in Table A-1 in Appendix A, Performance-Monitoring Events are model-specific for the Pentium® processor. 18.104.22.168. CONTROL AND EVENT SELECT REGISTER (CESR) The 32-bit control and event select MSR (CESR) is used to control the operation of performance-monitoring counters CTR0 and CTR1 and their associated pins (refer to Figure 15-3). To control each counter, the CESR register contains a 6-bit event select field (ES0 and ES1), a pin control flag (PC0 and PC1), and a 3-bit counter control field (CC0 and CC1). The functions of these fields are as follows: ES0 and ES1 (event select) fields (bits 0 through 5, bits 16 through 21) Selects (by entering an event code in the field) up to two events to be monitored. Refer to Table A-1 in Appendix A, Performance-Monitoring Events for a list of available event codes CC0 and CC1 (counter control) fields (bits 6 through 8, bits 22 through 24) Controls the operation of the counter. The possible control codes are as follows: CCn 000 001 010 011 100 101 110 111 Meaning Count nothing (counter disabled) Count the selected event while CPL is 0, 1, or 2 Count the selected event while CPL is 3 Count the selected event regardless of CPL Count nothing (counter disabled) Count clocks (duration) while CPL is 0, 1, or 2 Count clocks (duration) while CPL is 3 Count clocks (duration) regardless of CPL 15-20 DEBUGGING AND PERFORMANCE MONITORING Note that...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.
- Spring '10