IntelSoftwareDevelopersManual

4 clears the vm flag in the eflags register 5 begins

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Unformatted text preview: xtensions are enabled. Class 3—All software-generated interrupts, that is interrupts generated with the INT n instruction1. • • The method the processor uses to handle class 2 and 3 interrupts depends on the setting of the following flags and fields: • IOPL field (bits 12 and 13 in the EFLAGS register)—Controls how class 3 software interrupts are handled when the processor is in virtual-8086 mode (refer to Section 2.3., “System Flags and Fields in the EFLAGS Register”, in Chapter 2, System Architecture Overview). This field also controls the enabling of the VIF and VIP flags in the EFLAGS register when the VME flag is set. The VIF and VIP flags are provided to assist in the handling of class 2 maskable hardware interrupts. VME flag (bit 0 in control register CR4)—Enables the virtual mode extension for the processor when set (refer to Section 2.5., “Control Registers”, in Chapter 2, System Architecture Overview). Software interrupt redirection bit map (32 bytes in the TSS, refer to Figure 16-5)—Contains 256 flags that indicates how class 3 software interrupts should be handled when they occur in virtual-8086 mode. A software interrupt can be directed either to the interrupt and exception handlers in the currently running 8086 program or to the protectedmode interrupt and exception handlers. The virtual interrupt flag (VIF) and virtual interrupt pending flag (VIP) in the EFLAGS register—Provides virtual interrupt support for the handling of class 2 maskable hardware interrupts (refer to Section 16.3.2., “Class 2—Maskable Hardware Interrupt Handling in Virtual-8086 Mode Using the Virtual Interrupt Mechanism”). NOTE • • • The VME flag, software interrupt redirection bit map, and VIF and VIP flags are only available in Intel Architecture processors that support the virtual mode extensions. These extensions were introduced in the Intel Architecture with the Pentium® processor. The following sections describe the actions that processor takes and the possible actions of interrupt and exception handlers for the two classes of interrupts described in the previous paragraphs. These sections describe three possible types of interrupt and exception handlers: 1. The INT 3 instruction is a special case (refer to the description of the INT n instruction in Chapter 3, Instruction Set Reference, of the Intel Architecture Software Developer’s Manual, Volume 2). 16-16 8086 EMULATION • • Protected-mode interrupt and exceptions handlers—These are the handlers that the processor calls through the protected-mode IDT. Virtual-8086 monitor interrupt and exception handlers—These handlers are resident in the virtual-8086 monitor, and they are commonly accessed through a general-protection exception (#GP, interrupt 13) that is directed to the protected-mode general-protection exception handler. 8086 program interrupt and exception handlers—These handlers are part of the 8086 program that is running in virtual-8086 mode. • The following sections describe how these handlers are used, depending on the selected class and method of interrupt and exception handling. 16.3.1. Class 1—Hardware Interrupt and Exception Handling in Virtual-8086 Mode In virtual-8086 mode, the Pentium® and P6 family processors handle hardware interrupts and exceptions in the same manner as they are handled by the Intel486™ and Intel386™ processors. They invoke the protected-mode interrupt or exception handler that the interrupt or exception vector points to in the IDT. Here, the IDT entry must contain either a 32-bit trap or interrupt gate or a task gate. The following sections describe various ways that a virtual-8086 mode interrupt or exception can be handled after the protected-mode handler has been invoked. Refer to Section 16.3.2., “Class 2—Maskable Hardware Interrupt Handling in Virtual-8086 Mode Using the Virtual Interrupt Mechanism” for a description of the virtual interrupt mechanism that is available for handling maskable hardware interrupts while in virtual-8086 mode. When this mechanism is either not available or not enabled, maskable hardware interrupts are handled in the same manner as exceptions, as described in the following sections. 16.3.1.1. HANDLING AN INTERRUPT OR EXCEPTION THROUGH A PROTECTED-MODE TRAP OR INTERRUPT GATE When an interrupt or exception vector points to a 32-bit trap or interrupt gate in the IDT, the gate must in turn point to a nonconforming, privilege-level 0, code segment. When accessing this code segment, the processor performs the following steps. 1. Switches to 32-bit protected mode and privilege level 0. 2. Saves the state of the processor on the privilege-level 0 stack. The states of the EIP, CS, EFLAGS, ESP, SS, ES, DS, FS, and GS registers are saved (refer to Figure 16-4). 3. Clears the segment registers. Saving the DS, ES, FS, and GS registers on the stack and then clearing the registers lets the interrupt or exception handler safely save and restore these registers regardless of the type segment selectors they contain...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

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