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5 33 interrupt and exception handling interrupt

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Unformatted text preview: ptions Serially Generate a Double Fault If another exception occurs while attempting to call the double-fault handler, the processor enters shutdown mode. This mode is similar to the state following execution of an HLT instruction. In this mode, the processor stops executing instructions until an NMI interrupt, SMI interrupt, hardware reset, or INIT# is received. The processor generates a special bus cycle to indicate that it has entered shutdown mode. Software designers may need to be aware of the response of hardware to receiving this signal. For example, hardware may turn on an indicator light on the front panel, generate an NMI interrupt to record diagnostic information, invoke reset initialization, generate an INIT initialization, or generate an SMI. If the shutdown occurs while the processor is executing an NMI interrupt handler, then only a hardware reset can restart the processor. Exception Error Code Zero. The processor always pushes an error code of 0 onto the stack of the double-fault handler. Saved Instruction Pointer The saved contents of CS and EIP registers are undefined. Program State Change A program-state following a double-fault exception is undefined. The program or task cannot be resumed or restarted. The only available action of the double-fault exception handler is to collect all possible context information for use in diagnostics and then close the application and/or shut down or reset the processor. 5-33 INTERRUPT AND EXCEPTION HANDLING Interrupt 9—Coprocessor Segment Overrun Exception Class Abort. (Intel reserved; do not use. Recent Intel Architecture processors do not generate this exception.) Description Indicates that an Intel386™ CPU-based systems with an Intel 387 math coprocessor detected a page or segment violation while transferring the middle portion of an Intel 387 math coprocessor operand. The P6 family, Pentium®, and Intel486™ processors do not generate this exception; instead, this condition is detected with a general protection exception (#GP), interrupt 13. Exception Error Code None. Saved Instruction Pointer The saved contents of CS and EIP registers point to the instruction that generated the exception. Program State Change A program-state following a coprocessor segment-overrun exception is undefined. The program or task cannot be resumed or restarted. The only available action of the exception handler is to save the instruction pointer and reinitialize the FPU using the FNINIT instruction. 5-34 INTERRUPT AND EXCEPTION HANDLING Interrupt 10—Invalid TSS Exception (#TS) Exception Class Description Indicates that a task switch was attempted and that invalid information was detected in the TSS for the target task. Table 5-6 shows the conditions that will cause an invalid-TSS exception to be generated. In general, these invalid conditions result from protection violations for the TSS descriptor; the LDT pointed to by the TSS; or the stack, code, or data segments referenced by the TSS. Table 5-6. Invalid TSS Conditions Error Code Index TSS segment selector index LDT segment selector index Stack-segment selector index Stack-segment selector index Stack-segment selector index Stack-segment selector index Code-segment selector index Code-segment selector index Code-segment selector index Code-segment selector index Data-segment selector index Data-segment selector index Invalid Condition TSS segment limit less than 67H for 32-bit TSS or less than 2CH for 16bit TSS. Invalid LDT or LDT not present Stack-segment selector exceeds descriptor table limit Stack segment is not writable Stack segment DPL ≠ CPL Stack-segment selector RPL ≠ CPL Code-segment selector exceeds descriptor table limit Code segment is not executable Nonconforming code segment DPL ≠ CPL Conforming code segment DPL greater than CPL Data-segment selector exceeds descriptor table limit Data segment not readable Fault. This exception can generated either in the context of the original task or in the context of the new task (refer to Section 6.3., “Task Switching” in Chapter 6, Task Management). Until the processor has completely verified the presence of the new TSS, the exception is generated in the context of the original task. Once the existence of the new TSS is verified, the task switch is considered complete. Any invalid-TSS conditions detected after this point are handled in the context of the new task. (A task switch is considered complete when the task register is loaded with the segment selector for the new TSS and, if the switch is due to a procedure call or interrupt, the previous task link field of the new TSS references the old TSS.) To insure that a valid TSS is available to process the exception, the invalid-TSS exception handler must be a task called using a task gate. 5-35 INTERRUPT AND EXCEPTION HANDLING Exception Error Code An error code containing the segment selector index for the segment descriptor that caused the violation is pushed onto the stack of the exception handler. If the EXT flag is set, it indicates t...
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