IntelSoftwareDevelopersManual

5 49 interrupt and exception handling interrupt

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Unformatted text preview: Software Developer’s Manual, Volume 1, for more information on handling floating-point-error exceptions. Exception Error Code None. The FPU provides its own error information. Saved Instruction Pointer The saved contents of CS and EIP registers point to the floating-point or WAIT/FWAIT instruction that was about to be executed when the floating-point-error exception was generated. This is not the faulting instruction in which the error condition was detected. The address of the faulting instruction is contained in the FPU instruction pointer register. Refer to “The FPU Instruction and Operand (Data) Pointers” in Chapter 7 of the Intel Architecture Software Developer’s Manual, Volume 1, for more information about information the FPU saves for use in handling floating-point-error exceptions. Program State Change A program-state change generally accompanies a floating-point-error exception because the handling of the exception is delayed until the next waiting floating-point or WAIT/FWAIT instruction following the faulting instruction. The FPU, however, saves sufficient information about the error condition to allow recovery from the error and re-execution of the faulting instruction if needed. In situations where nonfloating-point instructions depend on the results of a floating-point instruction, a WAIT or FWAIT instruction can be inserted in front of a dependent instruction to force a pending floating-point-error exception to be handled before the dependent instruction is executed. Refer to “Floating-Point Exception Synchronization” in Chapter 7 of the Intel Architecture Software Developer’s Manual, Volume 1, for more information about synchronization of floating-point-error exceptions. 5-49 INTERRUPT AND EXCEPTION HANDLING Interrupt 17—Alignment Check Exception (#AC) Exception Class Description Indicates that the processor detected an unaligned memory operand when alignment checking was enabled. Alignment checks are only carried out in data (or stack) segments (not in code or system segments). An example of an alignment-check violation is a word stored at an odd byte address, or a doubleword stored at an address that is not an integer multiple of 4. Table 5-7 lists the alignment requirements various data types recognized by the processor. Table 5-7. Alignment Requirements by Data Type Data Type Word Doubleword Single Real Double Real Extended Real Segment Selector 32-bit Far Pointer 48-bit Far Pointer 32-bit Pointer GDTR, IDTR, LDTR, or Task Register Contents FSTENV/FLDENV Save Area FSAVE/FRSTOR Save Area Bit String 128-bit 1 Fault. Address Must Be Divisible By 2 4 4 8 8 2 2 4 4 4 4 or 2, depending on operand size 4 or 2, depending on operand size 2 or 4 depending on the operand-size attribute. 16 1. 128-bit datatype introduced with the Pentium® III processor. This type of alignment check is done for operands less than 128-bits in size: 32-bit scalar single and 16-bit/32-bit/64-bit integer MMX™ technology; 2, 4, or 8 byte alignments checks are possible when #AC is enabled. Some exceptional cases are: • • The MOVUPS instruction, which performs a 128-bit unaligned load or store. In this case, 2/4/8-byte misalignments will be detected, but detection of 16-byte misalignment is not guaranteed and may vary with implementation. The FXSAVE/FXRSTOR instructions - refer to instruction descriptions To enable alignment checking, the following conditions must be true: • • • AM flag in CR0 register is set. AC flag in the EFLAGS register is set. The CPL is 3 (protected mode or virtual-8086 mode). 5-50 INTERRUPT AND EXCEPTION HANDLING Alignment-check faults are generated only when operating at privilege level 3 (user mode). Memory references that default to privilege level 0, such as segment descriptor loads, do not generate alignment-check faults, even when caused by a memory reference made from privilege level 3. Storing the contents of the GDTR, IDTR, LDTR, or task register in memory while at privilege level 3 can generate an alignment-check fault. Although application programs do not normally store these registers, the fault can be avoided by aligning the information stored on an even word-address. FSAVE and FRSTOR instructions generate unaligned references which can cause alignmentcheck faults. These instructions are rarely needed by application programs. Exception Error Code Yes (always zero). Saved Instruction Pointer The saved contents of CS and EIP registers point to the instruction that generated the exception. Program State Change A program-state change does not accompany an alignment-check fault, because the instruction is not executed. 5-51 INTERRUPT AND EXCEPTION HANDLING Interrupt 18—Machine-Check Exception (#MC) Exception Class Description Indicates that the processor detected an internal machine error or a bus error, or that an external agent detected a bus error. The machine-check exception is model-specific, available only on the P6 family and Pentium® processors. The implementation of the machine-check exception i...
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