Unformatted text preview: or systems, it communicates with an external I/O APIC chip. The external I/O APIC receives external interrupt events from the system and interprocessor interrupts from the processors on the system bus and distributes them to the processors on the system bus. The I/O APIC is part of Intel’s system chip set. Figure 7-2 shows the relationship of the local APICs on the processors in a multiple-processor (MP) system and the I/O APIC. The local APIC controls the dispatching of interrupts (to its associated processor) that it receives either locally or from the I/O APIC. It provides facilities for queuing, nesting and masking of interrupts. It handles the interrupt delivery protocol with its local processor and accesses to APIC registers, and also manages interprocessor interrupts and remote APIC register reads. A timer on the local APIC allows local generation of interrupts, and local interrupt pins permit local reception of processor-specific interrupts. The local APIC can be disabled and used in conjunction with a standard 8259A-style interrupt controller. (Disabling the local APIC can be done in hardware for the Pentium® processors or in software for the P6 family processors.) The I/O APIC is responsible for receiving interrupts generated by I/O devices and distributing them among the local APICs by means of the APIC Bus. The I/O APIC manages interrupts using either static or dynamic distribution schemes. Dynamic distribution of interrupts allows routing of interrupts to the lowest priority processors. It also handles the distribution of interprocessor interrupts and system-wide control functions such as NMI, INIT, SMI and start-up-interprocessor interrupts. Individual pins on the I/O APIC can be programmed to generate a specific, prioritized interrupt vector when asserted. The I/O APIC also has a “virtual wire mode” that allows it to cooperate with an external 8259A in the system. The APIC in the Pentium® and P6 family processors is an architectural subset of the Intel 82489DX external APIC. The differences are described in Section 7.5.19., “Software Visible Differences Between the Local APIC and the 82489DX” The following sections focus on the local APIC, and its implementation in the P6 family processors. Contact Intel for the information on I/O APIC. 7-13 MULTIPLE-PROCESSOR MANAGEMENT Processor #1 CPU Local APIC Local Interrupts Processor #2 CPU Local APIC Local Interrupts Processor #3 CPU Local APIC Local Interrupts APIC Bus I/O APIC External Interrupts I/O Chip Set Figure 7-2. I/O APIC and Local APICs in Multiple-Processor Systems 7.5.1. Presence of APIC Beginning with the P6 family processors, the presence or absence of an on-chip APIC can be detected using the CPUID instruction. When the CPUID instruction is executed, bit 9 of the feature flags returned in the EDX register indicates the presence (set) or absence (clear) of an on-chip local APIC. 7.5.2. Enabling or Disabling the Local APIC For the P6 family processors, a flag (the E flag, bit 11) in the APIC_BASE_MSR register permits the local APIC to be explicitly enabled or disabled. Refer to Section 7.5.8., “Relocation of the APIC Registers Base Address” for a description of this flag. For the Pentium® processor, the APICEN pin (which is shared with the PICD1 pin) is used during reset to enable or disable the local APIC. 7.5.3. APIC Bus All I/O APIC and local APICs communicate through the APIC bus (a 3-line inter-APIC bus). Two of the lines are open-drain (wired-OR) and are used for data transmission; the third line is a clock. The bus and its messages are invisible to software and are not classed as architectural (that is, the APIC bus and message format may change in future implementations without having any effect on software compatibility). 7-14 MULTIPLE-PROCESSOR MANAGEMENT 7.5.4. Valid Interrupts The local and I/O APICs support 240 distinct vectors in the range of 16 to 255. Interrupt priority is implied by its vector, according to the following relationship: priority = vector / 16 One is the lowest priority and 15 is the highest. Vectors 16 through 31 are reserved for exclusive use by the processor. The remaining vectors are for general use. The processor’s local APIC includes an in-service entry and a holding entry for each priority level. To avoid losing interrupts, software should allocate no more than 2 interrupt vectors per priority. 7.5.5. Interrupt Sources The local APIC can receive interrupts from the following sources: • • • • • • Interrupt pins on the processor chip, driven by locally connected I/O devices. A bus message from the I/O APIC, originated by an I/O device connected to the I/O APIC. A bus message from another processor’s local APIC, originated as an interprocessor interrupt. The local APIC’s programmable timer or the error register, through the self-interrupt generating mechanism. Software, through the self-interrupt generating mechanism. (P6 family processors.) The performance-monitoring c...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.
- Spring '10