Unformatted text preview: ounters. The local APIC services the I/O APIC and interprocessor interrupts according to the information included in the bus message (such as vector, trigger type, interrupt destination, etc.). Interpretation of the processor’s interrupt pins and the timer-generated interrupts is programmable, by means of the local vector table (LVT). To generate an interprocessor interrupt, the source processor programs its interrupt command register (ICR). The programming of the ICR causes generation of a corresponding interrupt bus message. Refer to Section 7.5.11., “Local Vector Table” and Section 7.5.12., “Interprocessor and Self-Interrupts” for detailed information on programming the LVT and ICR, respectively. 7.5.6. Bus Arbitration Overview Being connected on a common bus (the APIC bus), the local and I/O APICs have to arbitrate for permission to send a message on the APIC bus. Logically, the APIC bus is a wired-OR connection, enabling more than one local APIC to send messages simultaneously. Each APIC issues its arbitration priority at the beginning of each message, and one winner is collectively selected following an arbitration round. At any given time, a local APIC’s the arbitration priority is a unique value from 0 to 15. The arbitration priority of each local APIC is dynamically modified after each successfully transmitted message to preserve fairness. Refer to Section 7.5.16., “APIC Bus Arbitration Mechanism and Protocol” for a detailed discussion of bus arbitration. 7-15 MULTIPLE-PROCESSOR MANAGEMENT Section 7.5.3., “APIC Bus” describes the existing arbitration protocols and bus message formats, while Section 7.5.12., “Interprocessor and Self-Interrupts” describes the INIT level deassert message, used to resynchronize all local APICs’ arbitration IDs. Note that except for startup (refer to Section 7.5.11., “Local Vector Table”), all bus messages failing during delivery are automatically retried. The software should avoid situations in which interrupt messages may be “ignored” by disabled or nonexistent “target” local APICs, and messages are being resent repeatedly. 7.5.7. The Local APIC Block Diagram Figure 7-3 gives a functional block diagram for the local APIC. Software interacts with the local APIC by reading and writing its registers. The registers are memory-mapped to the processor’s physical address space, and for each processor they have an identical address space of 4 KBytes starting at address FEE00000H. (Refer to Section 7.5.8., “Relocation of the APIC Registers Base Address” for information on relocating the APIC registers base address for the P6 family processors.)
NOTE For P6 family processors, the APIC handles all memory accesses to addresses within the 4-KByte APIC register space and no external bus cycles are produced. For the Pentium® processors with an on-chip APIC, bus cycles are produced for accesses to the 4-KByte APIC register space. Thus, for software intended to run on Pentium® processors, system software should explicitly not map the APIC register space to regular system memory. Doing so can result in an invalid opcode exception (#UD) being generated or unpredictable execution. The 4-KByte APIC register address space should be mapped as uncacheable (UC), refer to Section 9, “Memory Cache Control”, in Chapter 9, Memory Cache Control. 7-16 MULTIPLE-PROCESSOR MANAGEMENT DATA/ADDR Version Register Timer Current Count Register Initial Count Register Divide Configuration Register Local Vec Table Timer
LINT0/1 15 TSR INTA EXTINT INTR EOI Register Task Priority Register Prioritizer Local Interrupts 0,1 Performance Monitoring Counters* Error V TSR 1 V TMR, ISR, IRR Registers TR V TR V Software Transparent Registers
Vec[3:0] & TMR Bit Register Select Interrupt Command Register Arb. ID Register Vector Decode APIC ID Register Logical Destination Register Destination Format Register Processor Priority Acceptance Logic INIT, NMI, SMI Dest. Mode & Vector APIC Bus Send/Receive Logic APIC Serial Bus * Available only in P6 family processors Figure 7-3. Local APIC Structure Within the 4-KByte APIC register area, the register address allocation scheme is shown in Table 7-1. Register offsets are aligned on 128-bit boundaries. All registers must be accessed using 32bit loads and stores. Wider registers (64-bit or 256-bit) are defined and accessed as independent multiple 32-bit registers. If a LOCK prefix is used with a MOV instruction that accesses the APIC address space, the prefix is ignored; that is, a locking operation does not take place. 7-17 MULTIPLE-PROCESSOR MANAGEMENT Table 7-1. Local APIC Register Address Map
Address FEE0 0000H FEE0 0010H FEE0 0020H FEE0 0030H FEE0 0040H FEE0 0050H FEE0 0060H FEE0 0070H FEE0 0080H FEE0 0090H FEE0 00A0H FEE0 00B0H FEE0 00C0H FEE0 00D0H FEE0 00E0H FEE0 00F0H FEE0 0100H through FEE0 0170H FEE0 0180H through FEE0 01F0H FEE0 0200H through FEE0 0270H FEE0 0280H FEE0 0290H through FEE0 02F0H FEE0 0300H FEE0 0310H FEE0 0320H FEE0 0330H FEE0 0340H FEE0 0350H FEE0 0360H FEE0 0370H FEE0 0380H 7-18 Reserved Reserved Local APIC ID Register Local APIC Version Register Reserved Reserved Reserved Res...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.
- Spring '10