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Unformatted text preview: the reporting of a divide-by-zero exception generated by another sub-operand. Table 5-2 shows the precedence for Streaming SIMD Extensions numeric exceptions. The table reflects the order in which interrupts are handled upon simultaneous recognition by the processor (for example, when multiple interrupts are pending at an instruction boundary). However, the table does not necessarily reflect the
5-10 INTERRUPT AND EXCEPTION HANDLING order in which interrupts will be recognized by the processor if received simultaneously at the processor pins.
Table 5-2. SIMD Floating-Point Exceptions Priority
Priority 1(Highest) Description Invalid operation exception due to SNaN operand (or any NaN operand for max, min, or certain compare and convert operations) QNaN operand1 Any other invalid operation exception not mentioned above or a divide-by-zero exception2 Denormal operand exception2 Numeric overflow and underflow exceptions possibly in conjunction with the inexact result exception2 Inexact result exception 2 3 4 5 6(Lowest) 1. Though this is not an exception, the handling of a QNaN operand has precedence over lower priority exceptions. For example, a QNaN divided by zero results in a QNaN, not a zero-divide exception. 2. If masked, then instruction execution continues, and a lower priority exception can occur as well. 5.8. INTERRUPT DESCRIPTOR TABLE (IDT) The interrupt descriptor table (IDT) associates each exception or interrupt vector with a gate descriptor for the procedure or task used to service the associated exception or interrupt. Like the GDT and LDTs, the IDT is an array of 8-byte descriptors (in protected mode). Unlike the GDT, the first entry of the IDT may contain a descriptor. To form an index into the IDT, the processor scales the exception or interrupt vector by eight (the number of bytes in a gate descriptor). Because there are only 256 interrupt or exception vectors, the IDT need not contain more than 256 descriptors. It can contain fewer than 256 descriptors, because descriptors are required only for the interrupt and exception vectors that may occur. All empty descriptor slots in the IDT should have the present flag for the descriptor set to 0. 5-11 INTERRUPT AND EXCEPTION HANDLING Table 5-3. Priority Among Simultaneous Exceptions and Interrupts
Priority 1 (Highest) Descriptions Hardware Reset and Machine Checks - RESET - Machine Check Trap on Task Switch - T flag in TSS is set External Hardware Interventions - FLUSH - STOPCLK - SMI - INIT Traps on the Previous Instruction - Breakpoints - Debug Trap Exceptions (TF flag set or data/I-O breakpoint) External Interrupts - NMI Interrupts - Maskable Hardware Interrupts Faults from Fetching Next Instruction - Code Breakpoint Fault - Code-Segment Limit Violation1 - Code Page Fault1 Faults from Decoding the Next Instruction - Instruction length > 15 bytes - Illegal Opcode - Coprocessor Not Available Faults on Executing an Instruction - Floating-point exception - Overflow - Bound error - Invalid TSS - Segment Not Present - Stack fault - General Protection - Data Page Fault - Alignment Check - SIMD floating-point exception 2 3 4 5 6 7 8 (Lowest) NOTE: 1. For the Pentium® and Intel486™ processors, the Code Segment Limit Violation and the Code Page Fault exceptions are assigned to the priority 7. The base addresses of the IDT should be aligned on an 8-byte boundary to maximize performance of cache line fills. The limit value is expressed in bytes and is added to the base address to get the address of the last valid byte. A limit value of 0 results in exactly 1 valid byte. Because IDT entries are always eight bytes long, the limit should always be one less than an integral multiple of eight (that is, 8N – 1). 5-12 INTERRUPT AND EXCEPTION HANDLING The IDT may reside anywhere in the linear address space. As shown in Figure 5-1, the processor locates the IDT using the IDTR register. This register holds both a 32-bit base address and 16-bit limit for the IDT. IDTR Register
47 16 15 0 IDT Base Address IDT Limit + Interrupt Descriptor Table (IDT)
Gate for Interrupt #n (n−1)∗8 Gate for Interrupt #3 Gate for Interrupt #2 Gate for Interrupt #1 31 0 16 8 0 Figure 5-1. Relationship of the IDTR and IDT The LIDT (load IDT register) and SIDT (store IDT register) instructions load and store the contents of the IDTR register, respectively. The LIDT instruction loads the IDTR register with the base address and limit held in a memory operand. This instruction can be executed only when the CPL is 0. It normally is used by the initialization code of an operating system when creating an IDT. An operating system also may use it to change from one IDT to another. The SIDT instruction copies the base and limit value stored in IDTR to memory. This instruction can be executed at any privilege level. If a vector references a descriptor beyond the limit of the IDT, a general-protection exception (#GP) is generated. 5.9. IDT DESCRIPTORS The IDT may contain any of three kinds of gate descriptors: • • • Task-gate descriptor Interrupt-gate descriptor Trap-gate descriptor 5-13 INTERR...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.
- Spring '10